sine.map.rpt

原创：采用VHDL语言编写的正弦信号发生器。rom采用quartus自带的lpm生成

; Name                                                                                                          ; Type ; Mode           ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF       ;
+---------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+------+-----------+
; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1|ALTSYNCRAM ; AUTO ; True Dual Port ; 64           ; 8            ; 64           ; 8            ; 512  ; SDATA.hex ;
+---------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+------+-----------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 109   ;
; Number of registers using Synchronous Clear  ; 23    ;
; Number of registers using Synchronous Load   ; 6     ;
; Number of registers using Asynchronous Clear ; 54    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 64    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; sld_hub:sld_hub_inst|hub_tdo           ; 2       ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                                                                                                          ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                                                                                                                ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 3:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; Yes        ; |sine|sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[4]                                                                                                                            ;
; 5:1                ; 5 bits    ; 15 LEs        ; 5 LEs                ; 10 LEs                 ; Yes        ; |sine|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]                                                                                                        ;
; 20:1               ; 4 bits    ; 52 LEs        ; 32 LEs               ; 20 LEs                 ; Yes        ; |sine|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0]                                                                                                             ;
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]                                                ;
; 5:1                ; 5 bits    ; 15 LEs        ; 5 LEs                ; 10 LEs                 ; Yes        ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|word_counter[1] ;
; 24:1               ; 4 bits    ; 64 LEs        ; 48 LEs               ; 16 LEs                 ; Yes        ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[2]      ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Source assignments for rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1 ;
+---------------------------------+--------------------+------+-------------------------------------------------------------+
; Assignment                      ; Value              ; from ; to                                                          ;
+---------------------------------+--------------------+------+-------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                           ;
+---------------------------------+--------------------+------+-------------------------------------------------------------+


+--------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: rom1:u1|altsyncram:altsyncram_component ;
+------------------------------------+-----------------+-------------------------------+
; Parameter Name                     ; Value           ; Type                          ;
+------------------------------------+-----------------+-------------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                       ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                    ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                  ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                  ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                ;
; OPERATION_MODE                     ; ROM             ; Untyped                       ;
; WIDTH_A                            ; 8               ; Integer                       ;
; WIDTHAD_A                          ; 6               ; Integer                       ;
; NUMWORDS_A                         ; 64              ; Integer                       ;
; OUTDATA_REG_A                      ; CLOCK0          ; Untyped                       ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                       ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                       ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                       ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                       ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                       ;
; WIDTH_B                            ; 1               ; Untyped                       ;
; WIDTHAD_B                          ; 1               ; Untyped                       ;
; NUMWORDS_B                         ; 1               ; Untyped                       ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                       ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                       ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                       ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                       ;
; OUTDATA_REG_B                      ; UNREGISTERED    ; Untyped                       ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                       ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                       ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                       ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                       ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                       ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                       ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                       ;
; WIDTH_BYTEENA_A                    ; 1               ; Integer                       ;
; WIDTH_BYTEENA_B                    ; 1               ; Untyped                       ;
; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                       ;
; BYTE_SIZE                          ; 8               ; Untyped                       ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                       ;
; INIT_FILE                          ; SDATA.hex       ; Untyped                       ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                       ;
; MAXIMUM_DEPTH                      ; 0               ; Untyped                       ;
; CLOCK_ENABLE_INPUT_A               ; BYPASS          ; Untyped                       ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                       ;
; CLOCK_ENABLE_OUTPUT_A              ; BYPASS          ; Untyped                       ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                       ;
; DEVICE_FAMILY                      ; Cyclone II      ; Untyped                       ;
; CBXI_PARAMETER                     ; altsyncram_4d51 ; Untyped                       ;
+------------------------------------+-----------------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2 ;
+-----------------------+------------+----------------------------------------------------------------------------------------------------------+
; Parameter Name        ; Value      ; Type                                                                                                     ;
+-----------------------+------------+----------------------------------------------------------------------------------------------------------+
; sld_node_info         ; 135818752  ; Integer                                                                                                  ;