📄 sine.map.rpt
字号:
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Maximum Number of M4K Memory Blocks ; -1 ; -1 ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
+--------------------------------------------------------------------+--------------------+--------------------+
+-------------------------------------------------+
; Analysis & Synthesis Default Parameter Settings ;
+----------------------+--------------------------+
; Name ; Setting ;
+----------------------+--------------------------+
; CYCLONEII_SAFE_WRITE ; "VERIFIED_SAFE" ;
+----------------------+--------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------+
; rom1.vhd ; yes ; User VHDL File ; D:/quartus/myproject/正弦信号发生器/rom1.vhd ;
; sine.vhd ; yes ; User VHDL File ; D:/quartus/myproject/正弦信号发生器/sine.vhd ;
; altsyncram.tdf ; yes ; Megafunction ; c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf ;
; stratix_ram_block.inc ; yes ; Other ; c:/altera/quartus51/libraries/megafunctions/stratix_ram_block.inc ;
; lpm_mux.inc ; yes ; Other ; c:/altera/quartus51/libraries/megafunctions/lpm_mux.inc ;
; lpm_decode.inc ; yes ; Other ; c:/altera/quartus51/libraries/megafunctions/lpm_decode.inc ;
; aglobal51.inc ; yes ; Other ; c:/altera/quartus51/libraries/megafunctions/aglobal51.inc ;
; altsyncram.inc ; yes ; Other ; c:/altera/quartus51/libraries/megafunctions/altsyncram.inc ;
; a_rdenreg.inc ; yes ; Other ; c:/altera/quartus51/libraries/megafunctions/a_rdenreg.inc ;
; altrom.inc ; yes ; Other ; c:/altera/quartus51/libraries/megafunctions/altrom.inc ;
; altram.inc ; yes ; Other ; c:/altera/quartus51/libraries/megafunctions/altram.inc ;
; altdpram.inc ; yes ; Other ; c:/altera/quartus51/libraries/megafunctions/altdpram.inc ;
; altqpram.inc ; yes ; Other ; c:/altera/quartus51/libraries/megafunctions/altqpram.inc ;
; db/altsyncram_4d51.tdf ; yes ; Auto-Generated Megafunction ; D:/quartus/myproject/正弦信号发生器/db/altsyncram_4d51.tdf ;
; db/altsyncram_b192.tdf ; yes ; Auto-Generated Megafunction ; D:/quartus/myproject/正弦信号发生器/db/altsyncram_b192.tdf ;
; sld_mod_ram_rom.vhd ; yes ; Encrypted Megafunction ; c:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd ;
; sld_rom_sr.vhd ; yes ; Encrypted Megafunction ; c:/altera/quartus51/libraries/megafunctions/sld_rom_sr.vhd ;
; sld_hub.vhd ; yes ; Encrypted Megafunction ; c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd ;
; lpm_shiftreg.tdf ; yes ; Megafunction ; c:/altera/quartus51/libraries/megafunctions/lpm_shiftreg.tdf ;
; lpm_constant.inc ; yes ; Other ; c:/altera/quartus51/libraries/megafunctions/lpm_constant.inc ;
; dffeea.inc ; yes ; Other ; c:/altera/quartus51/libraries/megafunctions/dffeea.inc ;
; lpm_decode.tdf ; yes ; Megafunction ; c:/altera/quartus51/libraries/megafunctions/lpm_decode.tdf ;
; declut.inc ; yes ; Other ; c:/altera/quartus51/libraries/megafunctions/declut.inc ;
; altshift.inc ; yes ; Other ; c:/altera/quartus51/libraries/megafunctions/altshift.inc ;
; lpm_compare.inc ; yes ; Other ; c:/altera/quartus51/libraries/megafunctions/lpm_compare.inc ;
; db/decode_rpe.tdf ; yes ; Auto-Generated Megafunction ; D:/quartus/myproject/正弦信号发生器/db/decode_rpe.tdf ;
; sld_dffex.vhd ; yes ; Encrypted Megafunction ; c:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------+
+------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+--------------------------+
; Resource ; Usage ;
+---------------------------------------------+--------------------------+
; Total combinational functions ; 160 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 64 ;
; -- 3 input functions ; 42 ;
; -- <=2 input functions ; 54 ;
; -- Combinational cells for routing ; 0 ;
; Logic elements by mode ; ;
; -- normal mode ; 139 ;
; -- arithmetic mode ; 21 ;
; Total registers ; 109 ;
; I/O pins ; 9 ;
; Total memory bits ; 512 ;
; Maximum fan-out node ; altera_internal_jtag~TDO ;
; Maximum fan-out ; 133 ;
; Total fan-out ; 982 ;
; Average fan-out ; 3.37 ;
+---------------------------------------------+--------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+---------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+---------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; |sine ; 160 (10) ; 109 (6) ; 512 ; 0 ; 0 ; 0 ; 9 ; 0 ; |sine ;
; |rom1:u1| ; 60 (0) ; 33 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sine|rom1:u1 ;
; |altsyncram:altsyncram_component| ; 60 (0) ; 33 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sine|rom1:u1|altsyncram:altsyncram_component ;
; |altsyncram_4d51:auto_generated| ; 60 (0) ; 33 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated ;
; |altsyncram_b192:altsyncram1| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1 ;
; |sld_mod_ram_rom:mgl_prim2| ; 60 (32) ; 33 (24) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2 ;
; |sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr| ; 28 (28) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sine|rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr ;
; |sld_hub:sld_hub_inst| ; 90 (35) ; 70 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sine|sld_hub:sld_hub_inst ;
; |lpm_decode:instruction_decoder| ; 5 (0) ; 5 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sine|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder ;
; |decode_rpe:auto_generated| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sine|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated ;
; |lpm_shiftreg:jtag_ir_register| ; 0 (0) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sine|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register ;
; |sld_dffex:BROADCAST| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sine|sld_hub:sld_hub_inst|sld_dffex:BROADCAST ;
; |sld_dffex:IRF_ENA_0| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sine|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0 ;
; |sld_dffex:IRF_ENA| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sine|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA ;
; |sld_dffex:IRSR| ; 3 (3) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sine|sld_hub:sld_hub_inst|sld_dffex:IRSR ;
; |sld_dffex:RESET| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sine|sld_hub:sld_hub_inst|sld_dffex:RESET ;
; |sld_dffex:\GEN_IRF:1:IRF| ; 1 (1) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sine|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF ;
; |sld_dffex:\GEN_SHADOW_IRF:1:S_IRF| ; 0 (0) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sine|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF ;
; |sld_jtag_state_machine:jtag_state_machine| ; 20 (20) ; 19 (19) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sine|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine ;
; |sld_rom_sr:HUB_INFO_REG| ; 21 (21) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |sine|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG ;
+---------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+---------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+------+-----------+
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