sine.rpp.talkback.xml

原创：采用VHDL语言编写的正弦信号发生器。rom采用quartus自带的lpm生成

		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
		<load units="pF">0</load>
	</row>
	<row>
		<name>dout[4]</name>
		<pin__>J22</pin__>
		<i_o_bank>5</i_o_bank>
		<x_coordinate>65</x_coordinate>
		<y_coordinate>21</y_coordinate>
		<cell_number>2</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
		<load units="pF">0</load>
	</row>
	<row>
		<name>dout[5]</name>
		<pin__>L17</pin__>
		<i_o_bank>5</i_o_bank>
		<x_coordinate>65</x_coordinate>
		<y_coordinate>21</y_coordinate>
		<cell_number>1</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
		<load units="pF">0</load>
	</row>
	<row>
		<name>dout[6]</name>
		<pin__>J21</pin__>
		<i_o_bank>5</i_o_bank>
		<x_coordinate>65</x_coordinate>
		<y_coordinate>21</y_coordinate>
		<cell_number>3</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
		<load units="pF">0</load>
	</row>
	<row>
		<name>dout[7]</name>
		<pin__>K17</pin__>
		<i_o_bank>5</i_o_bank>
		<x_coordinate>65</x_coordinate>
		<y_coordinate>21</y_coordinate>
		<cell_number>0</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
		<load units="pF">0</load>
	</row>
</output_pins>
<i_o_bank_usage>
	<row>
		<i_o_bank>1</i_o_bank>
		<usage>1 / 46 ( 2 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
	<row>
		<i_o_bank>2</i_o_bank>
		<usage>2 / 39 ( 5 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
	<row>
		<i_o_bank>3</i_o_bank>
		<usage>0 / 39 ( 0 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
	<row>
		<i_o_bank>4</i_o_bank>
		<usage>0 / 36 ( 0 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
	<row>
		<i_o_bank>5</i_o_bank>
		<usage>8 / 44 ( 18 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
	<row>
		<i_o_bank>6</i_o_bank>
		<usage>1 / 43 ( 2 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
	<row>
		<i_o_bank>7</i_o_bank>
		<usage>0 / 36 ( 0 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
	<row>
		<i_o_bank>8</i_o_bank>
		<usage>0 / 39 ( 0 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
</i_o_bank_usage>
<in_system_memory_content_editor_settings>
	<row>
		<instance_index>0</instance_index>
		<instance_id>rom1</instance_id>
		<width>8</width>
		<depth>64</depth>
		<mode>Read/Write</mode>
		<hierarchy_location>rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated</hierarchy_location>
	</row>
</in_system_memory_content_editor_settings>
<advanced_data___general>
	<row>
		<name>Status Code</name>
		<value>0</value>
	</row>
	<row>
		<name>Desired User Slack</name>
		<value>0</value>
	</row>
	<row>
		<name>Fit Attempts</name>
		<value>1</value>
	</row>
</advanced_data___general>
<advanced_data___placement_preparation>
	<row>
		<name>Auto Fit Point 1 - Fit Attempt 1</name>
		<value>ff</value>
	</row>
	<row>
		<name>Mid Wire Use - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Mid Slack - Fit Attempt 1</name>
		<value>493145</value>
	</row>
	<row>
		<name>Internal Atom Count - Fit Attempt 1</name>
		<value>270</value>
	</row>
	<row>
		<name>LE/ALM Count - Fit Attempt 1</name>
		<value>178</value>
	</row>
	<row>
		<name>LAB Count - Fit Attempt 1</name>
		<value>21</value>
	</row>
	<row>
		<name>Outputs per Lab - Fit Attempt 1</name>
		<value>5.619</value>
	</row>
	<row>
		<name>Inputs per LAB - Fit Attempt 1</name>
		<value>8.714</value>
	</row>
	<row>
		<name>Global Inputs per LAB - Fit Attempt 1</name>
		<value>1.476</value>
	</row>
	<row>
		<name>LAB Constraint &apos;non-global clock + sync load&apos; - Fit Attempt 1</name>
		<value>0:20;1:1</value>
	</row>
	<row>
		<name>LAB Constraint &apos;non-global controls&apos; - Fit Attempt 1</name>
		<value>0:6;1:4;2:10;3:1</value>
	</row>
	<row>
		<name>LAB Constraint &apos;non-global + aclr&apos; - Fit Attempt 1</name>
		<value>0:5;1:3;2:4;3:7;4:2</value>
	</row>
	<row>
		<name>LAB Constraint &apos;global non-clock non-aclr&apos; - Fit Attempt 1</name>
		<value>0:21</value>
	</row>
	<row>
		<name>LAB Constraint &apos;global controls&apos; - Fit Attempt 1</name>
		<value>0:3;1:7;2:8;3:3</value>
	</row>
	<row>
		<name>LAB Constraint &apos;deterministic LABSMUXA/LABXMUXB&apos; - Fit Attempt 1</name>
		<value>0:9;1:10;2:2</value>
	</row>
	<row>
		<name>LAB Constraint &apos;deterministic LABSMUXC/LABXMUXD&apos; - Fit Attempt 1</name>
		<value>0:6;1:10;2:5</value>
	</row>
	<row>
		<name>LAB Constraint &apos;clock / ce pair constraint&apos; - Fit Attempt 1</name>
		<value>0:3;1:7;2:11</value>
	</row>
	<row>
		<name>LAB Constraint &apos;aclr constraint&apos; - Fit Attempt 1</name>
		<value>0:3;1:11;2:7</value>
	</row>
	<row>
		<name>LAB Constraint &apos;true sload_sclear pair&apos; - Fit Attempt 1</name>
		<value>0:11;1:10</value>
	</row>
	<row>
		<name>LAB Constraint &apos;constant sload_sclear pair&apos; - Fit Attempt 1</name>
		<value>0:14;1:7</value>
	</row>
	<row>
		<name>LAB Constraint &apos;has placement constraint&apos; - Fit Attempt 1</name>
		<value>0:21</value>
	</row>
	<row>
		<name>LEs in Chains - Fit Attempt 1</name>
		<value>26</value>
	</row>
	<row>
		<name>LEs in Long Chains - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>LABs with Chains - Fit Attempt 1</name>
		<value>5</value>
	</row>
	<row>
		<name>LABs with Multiple Chains - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Time - Fit Attempt 1</name>
		<value>1</value>
	</row>
	<row>
		<name>Time in tsm_dat.dll - Fit Attempt 1</name>
		<value>0.020</value>
	</row>
	<row>
		<name>Time in tsm_tan.dll - Fit Attempt 1</name>
		<value>0.200</value>
	</row>
</advanced_data___placement_preparation>
<advanced_data___placement>
	<row>
		<name>Auto Fit Point 2 - Fit Attempt 1</name>
		<value>ff</value>
	</row>
	<row>
		<name>Early Wire Use - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Early Slack - Fit Attempt 1</name>
		<value>495348</value>
	</row>
	<row>
		<name>Auto Fit Point 3 - Fit Attempt 1</name>
		<value>ff</value>
	</row>
	<row>
		<name>Mid Wire Use - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Mid Slack - Fit Attempt 1</name>
		<value>495361</value>
	</row>
	<row>
		<name>Auto Fit Point 4 - Fit Attempt 1</name>
		<value>ff</value>
	</row>
	<row>
		<name>Late Wire Use - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Late Slack - Fit Attempt 1</name>
		<value>495361</value>
	</row>
	<row>
		<name>Auto Fit Point 5 - Fit Attempt 1</name>
		<value>ff</value>
	</row>
	<row>
		<name>Time - Fit Attempt 1</name>
		<value>2</value>
	</row>
	<row>
		<name>Time in tsm_dat.dll - Fit Attempt 1</name>
		<value>0.020</value>
	</row>
	<row>
		<name>Time in tsm_tan.dll - Fit Attempt 1</name>
		<value>0.600</value>
	</row>
</advanced_data___placement>
<advanced_data___routing>
	<row>
		<name>Early Slack - Fit Attempt 1</name>
		<value>496085</value>
	</row>
	<row>
		<name>Early Wire Use - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Peak Regional Wire - Fit Attempt 1</name>
		<value>2</value>
	</row>
	<row>
		<name>Mid Slack - Fit Attempt 1</name>
		<value>493950</value>
	</row>
	<row>
		<name>Late Slack - Fit Attempt 1</name>
		<value>493950</value>
	</row>
	<row>
		<name>Late Slack - Fit Attempt 1</name>
		<value>493950</value>
	</row>
	<row>
		<name>Late Wire Use - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Time - Fit Attempt 1</name>
		<value>28</value>
	</row>
	<row>
		<name>Time in tsm_dat.dll - Fit Attempt 1</name>
		<value>0.010</value>
	</row>
	<row>
		<name>Time in tsm_tan.dll - Fit Attempt 1</name>
		<value>0.781</value>
	</row>
</advanced_data___routing>
</talkback>