disp.vhd

原创：基于VHDL语言编写的电子钟。采用模块化编写

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity disp is
port(
	clk1,rst:in std_logic;--扫描频率  约为10ms=100hz
	secl,sech,minl,minh,hourl,hourh:in std_logic_vector(3 downto 0);	--秒分时输入
	disp:out std_logic_vector(3 downto 0);
	dp:out std_logic;		--区分时分秒显示
	sel:out std_logic_vector(5 downto 0)		--位选输出
);
end entity disp;

architecture beh of disp is
signal count:std_logic_vector(2 downto 0);
begin
P1:	process(clk1,rst)
	begin
		if(rst='0')then
		count<="000";
		elsif(clk1'event and clk1='1')then
		 if(count="111")then
			count<="000";
			else
			count<=count+1;
			end if;
		 end if;
	end process P1;
P2:process(clk1,rst)
begin
	if(rst='0')then
		disp<="0000";
		dp<='0';
		sel<="000000";
	elsif(clk1'event and clk1='1')then
	case count is
		when "000"=>disp<=secl;dp<='1';sel<="000001";    --秒显示 
		when "001"=>disp<=sech;dp<='1';sel<="000010";
		when "010"=>disp<=minl;dp<='0';sel<="000100";	  --分显示
		when "011"=>disp<=minh;dp<='1';sel<="001000";
		when "100"=>disp<=hourl;dp<='0';sel<="010000";   --小时显示
		when "101"=>disp<=hourh;dp<='1';sel<="100000";	
		when others=>disp<="1111";dp<='1';sel<="000000";		--不显示
		end case;
	end if;
end process P2;
end architecture beh;