clock.tan.qmsg

原创：基于VHDL语言编写的电子钟。采用模块化编写

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "KEY_CHANGE register counter24:inst4\|l\[1\] register counter24:inst4\|l\[2\] 62.55 MHz 15.987 ns Internal " "Info: Clock \"KEY_CHANGE\" has Internal fmax of 62.55 MHz between source register \"counter24:inst4\|l\[1\]\" and destination register \"counter24:inst4\|l\[2\]\" (period= 15.987 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.643 ns + Longest register register " "Info: + Longest register to register delay is 3.643 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter24:inst4\|l\[1\] 1 REG LCFF_X42_Y14_N19 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X42_Y14_N19; Fanout = 8; REG Node = 'counter24:inst4\|l\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "" { counter24:inst4|l[1] } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "D:/quartus/myproject/clock/counter24.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.651 ns) 1.434 ns counter24:inst4\|LessThan~148 2 COMB LCCOMB_X42_Y14_N14 2 " "Info: 2: + IC(0.783 ns) + CELL(0.651 ns) = 1.434 ns; Loc. = LCCOMB_X42_Y14_N14; Fanout = 2; COMB Node = 'counter24:inst4\|LessThan~148'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "1.434 ns" { counter24:inst4|l[1] counter24:inst4|LessThan~148 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.370 ns) 2.198 ns counter24:inst4\|l\[3\]~841 3 COMB LCCOMB_X42_Y14_N24 4 " "Info: 3: + IC(0.394 ns) + CELL(0.370 ns) = 2.198 ns; Loc. = LCCOMB_X42_Y14_N24; Fanout = 4; COMB Node = 'counter24:inst4\|l\[3\]~841'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "0.764 ns" { counter24:inst4|LessThan~148 counter24:inst4|l[3]~841 } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "D:/quartus/myproject/clock/counter24.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.713 ns) + CELL(0.624 ns) 3.535 ns counter24:inst4\|l\[2\]~844 4 COMB LCCOMB_X42_Y14_N4 1 " "Info: 4: + IC(0.713 ns) + CELL(0.624 ns) = 3.535 ns; Loc. = LCCOMB_X42_Y14_N4; Fanout = 1; COMB Node = 'counter24:inst4\|l\[2\]~844'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "1.337 ns" { counter24:inst4|l[3]~841 counter24:inst4|l[2]~844 } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "D:/quartus/myproject/clock/counter24.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.643 ns counter24:inst4\|l\[2\] 5 REG LCFF_X42_Y14_N5 9 " "Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 3.643 ns; Loc. = LCFF_X42_Y14_N5; Fanout = 9; REG Node = 'counter24:inst4\|l\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "0.108 ns" { counter24:inst4|l[2]~844 counter24:inst4|l[2] } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "D:/quartus/myproject/clock/counter24.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.753 ns ( 48.12 % ) " "Info: Total cell delay = 1.753 ns ( 48.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.890 ns ( 51.88 % ) " "Info: Total interconnect delay = 1.890 ns ( 51.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "3.643 ns" { counter24:inst4|l[1] counter24:inst4|LessThan~148 counter24:inst4|l[3]~841 counter24:inst4|l[2]~844 counter24:inst4|l[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.643 ns" { counter24:inst4|l[1] counter24:inst4|LessThan~148 counter24:inst4|l[3]~841 counter24:inst4|l[2]~844 counter24:inst4|l[2] } { 0.000ns 0.783ns 0.394ns 0.713ns 0.000ns } { 0.000ns 0.651ns 0.370ns 0.624ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-12.080 ns - Smallest " "Info: - Smallest clock skew is -12.080 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "KEY_CHANGE destination 7.983 ns + Shortest register " "Info: + Shortest clock path from clock \"KEY_CHANGE\" to destination register is 7.983 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.924 ns) 0.924 ns KEY_CHANGE 1 CLK PIN_AB15 3 " "Info: 1: + IC(0.000 ns) + CELL(0.924 ns) = 0.924 ns; Loc. = PIN_AB15; Fanout = 3; CLK Node = 'KEY_CHANGE'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "" { KEY_CHANGE } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 40 8 176 56 "KEY_CHANGE" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.990 ns) + CELL(0.650 ns) 3.564 ns inst16 2 COMB LCCOMB_X43_Y12_N10 1 " "Info: 2: + IC(1.990 ns) + CELL(0.650 ns) = 3.564 ns; Loc. = LCCOMB_X43_Y12_N10; Fanout = 1; COMB Node = 'inst16'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "2.640 ns" { KEY_CHANGE inst16 } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 144 472 536 192 "inst16" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.562 ns) + CELL(0.000 ns) 6.126 ns inst16~clkctrl 3 COMB CLKCTRL_G5 6 " "Info: 3: + IC(2.562 ns) + CELL(0.000 ns) = 6.126 ns; Loc. = CLKCTRL_G5; Fanout = 6; COMB Node = 'inst16~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "2.562 ns" { inst16 inst16~clkctrl } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 144 472 536 192 "inst16" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.191 ns) + CELL(0.666 ns) 7.983 ns counter24:inst4\|l\[2\] 4 REG LCFF_X42_Y14_N5 9 " "Info: 4: + IC(1.191 ns) + CELL(0.666 ns) = 7.983 ns; Loc. = LCFF_X42_Y14_N5; Fanout = 9; REG Node = 'counter24:inst4\|l\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "1.857 ns" { inst16~clkctrl counter24:inst4|l[2] } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "D:/quartus/myproject/clock/counter24.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.240 ns ( 28.06 % ) " "Info: Total cell delay = 2.240 ns ( 28.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.743 ns ( 71.94 % ) " "Info: Total interconnect delay = 5.743 ns ( 71.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "7.983 ns" { KEY_CHANGE inst16 inst16~clkctrl counter24:inst4|l[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.983 ns" { KEY_CHANGE KEY_CHANGE~combout inst16 inst16~clkctrl counter24:inst4|l[2] } { 0.000ns 0.000ns 1.990ns 2.562ns 1.191ns } { 0.000ns 0.924ns 0.650ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "KEY_CHANGE source 20.063 ns - Longest register " "Info: - Longest clock path from clock \"KEY_CHANGE\" to source register is 20.063 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.924 ns) 0.924 ns KEY_CHANGE 1 CLK PIN_AB15 3 " "Info: 1: + IC(0.000 ns) + CELL(0.924 ns) = 0.924 ns; Loc. = PIN_AB15; Fanout = 3; CLK Node = 'KEY_CHANGE'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "" { KEY_CHANGE } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 40 8 176 56 "KEY_CHANGE" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.998 ns) + CELL(0.616 ns) 3.538 ns inst17~38 2 COMB LCCOMB_X43_Y12_N28 1 " "Info: 2: + IC(1.998 ns) + CELL(0.616 ns) = 3.538 ns; Loc. = LCCOMB_X43_Y12_N28; Fanout = 1; COMB Node = 'inst17~38'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "2.614 ns" { KEY_CHANGE inst17~38 } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 8 480 544 56 "inst17" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.238 ns) + CELL(0.000 ns) 6.776 ns inst17~38clkctrl 3 COMB CLKCTRL_G2 8 " "Info: 3: + IC(3.238 ns) + CELL(0.000 ns) = 6.776 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'inst17~38clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "3.238 ns" { inst17~38 inst17~38clkctrl } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 8 480 544 56 "inst17" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.174 ns) + CELL(0.970 ns) 8.920 ns counter60:inst\|cout 4 REG LCFF_X43_Y12_N3 2 " "Info: 4: + IC(1.174 ns) + CELL(0.970 ns) = 8.920 ns; Loc. = LCFF_X43_Y12_N3; Fanout = 2; REG Node = 'counter60:inst\|cout'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "2.144 ns" { inst17~38clkctrl counter60:inst|cout } "NODE_NAME" } "" } } { "counter60.vhd" "" { Text "D:/quartus/myproject/clock/counter60.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.437 ns) + CELL(0.206 ns) 9.563 ns inst15 5 COMB LCCOMB_X43_Y12_N4 1 " "Info: 5: + IC(0.437 ns) + CELL(0.206 ns) = 9.563 ns; Loc. = LCCOMB_X43_Y12_N4; Fanout = 1; COMB Node = 'inst15'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "0.643 ns" { counter60:inst|cout inst15 } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 88 472 536 136 "inst15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.202 ns) + CELL(0.000 ns) 11.765 ns inst15~clkctrl 6 COMB CLKCTRL_G6 8 " "Info: 6: + IC(2.202 ns) + CELL(0.000 ns) = 11.765 ns; Loc. = CLKCTRL_G6; Fanout = 8; COMB Node = 'inst15~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "2.202 ns" { inst15 inst15~clkctrl } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 88 472 536 136 "inst15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.190 ns) + CELL(0.970 ns) 13.925 ns counter60:inst3\|cout 7 REG LCFF_X43_Y14_N27 3 " "Info: 7: + IC(1.190 ns) + CELL(0.970 ns) = 13.925 ns; Loc. = LCFF_X43_Y14_N27; Fanout = 3; REG Node = 'counter60:inst3\|cout'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "2.160 ns" { inst15~clkctrl counter60:inst3|cout } "NODE_NAME" } "" } } { "counter60.vhd" "" { Text "D:/quartus/myproject/clock/counter60.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.095 ns) + CELL(0.624 ns) 15.644 ns inst16 8 COMB LCCOMB_X43_Y12_N10 1 " "Info: 8: + IC(1.095 ns) + CELL(0.624 ns) = 15.644 ns; Loc. = LCCOMB_X43_Y12_N10; Fanout = 1; COMB Node = 'inst16'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "1.719 ns" { counter60:inst3|cout inst16 } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 144 472 536 192 "inst16" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.562 ns) + CELL(0.000 ns) 18.206 ns inst16~clkctrl 9 COMB CLKCTRL_G5 6 " "Info: 9: + IC(2.562 ns) + CELL(0.000 ns) = 18.206 ns; Loc. = CLKCTRL_G5; Fanout = 6; COMB Node = 'inst16~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "2.562 ns" { inst16 inst16~clkctrl } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 144 472 536 192 "inst16" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.191 ns) + CELL(0.666 ns) 20.063 ns counter24:inst4\|l\[1\] 10 REG LCFF_X42_Y14_N19 8 " "Info: 10: + IC(1.191 ns) + CELL(0.666 ns) = 20.063 ns; Loc. = LCFF_X42_Y14_N19; Fanout = 8; REG Node = 'counter24:inst4\|l\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "1.857 ns" { inst16~clkctrl counter24:inst4|l[1] } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "D:/quartus/myproject/clock/counter24.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.976 ns ( 24.80 % ) " "Info: Total cell delay = 4.976 ns ( 24.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "15.087 ns ( 75.20 % ) " "Info: Total interconnect delay = 15.087 ns ( 75.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "20.063 ns" { KEY_CHANGE inst17~38 inst17~38clkctrl counter60:inst|cout inst15 inst15~clkctrl counter60:inst3|cout inst16 inst16~clkctrl counter24:inst4|l[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "20.063 ns" { KEY_CHANGE KEY_CHANGE~combout inst17~38 inst17~38clkctrl counter60:inst|cout inst15 inst15~clkctrl counter60:inst3|cout inst16 inst16~clkctrl counter24:inst4|l[1] } { 0.000ns 0.000ns 1.998ns 3.238ns 1.174ns 0.437ns 2.202ns 1.190ns 1.095ns 2.562ns 1.191ns } { 0.000ns 0.924ns 0.616ns 0.000ns 0.970ns 0.206ns 0.000ns 0.970ns 0.624ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "7.983 ns" { KEY_CHANGE inst16 inst16~clkctrl counter24:inst4|l[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.983 ns" { KEY_CHANGE KEY_CHANGE~combout inst16 inst16~clkctrl counter24:inst4|l[2] } { 0.000ns 0.000ns 1.990ns 2.562ns 1.191ns } { 0.000ns 0.924ns 0.650ns 0.000ns 0.666ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "20.063 ns" { KEY_CHANGE inst17~38 inst17~38clkctrl counter60:inst|cout inst15 inst15~clkctrl counter60:inst3|cout inst16 inst16~clkctrl counter24:inst4|l[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "20.063 ns" { KEY_CHANGE KEY_CHANGE~combout inst17~38 inst17~38clkctrl counter60:inst|cout inst15 inst15~clkctrl counter60:inst3|cout inst16 inst16~clkctrl counter24:inst4|l[1] } { 0.000ns 0.000ns 1.998ns 3.238ns 1.174ns 0.437ns 2.202ns 1.190ns 1.095ns 2.562ns 1.191ns } { 0.000ns 0.924ns 0.616ns 0.000ns 0.970ns 0.206ns 0.000ns 0.970ns 0.624ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "counter24.vhd" "" { Text "D:/quartus/myproject/clock/counter24.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "counter24.vhd" "" { Text "D:/quartus/myproject/clock/counter24.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "3.643 ns" { counter24:inst4|l[1] counter24:inst4|LessThan~148 counter24:inst4|l[3]~841 counter24:inst4|l[2]~844 counter24:inst4|l[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.643 ns" { counter24:inst4|l[1] counter24:inst4|LessThan~148 counter24:inst4|l[3]~841 counter24:inst4|l[2]~844 counter24:inst4|l[2] } { 0.000ns 0.783ns 0.394ns 0.713ns 0.000ns } { 0.000ns 0.651ns 0.370ns 0.624ns 0.108ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "7.983 ns" { KEY_CHANGE inst16 inst16~clkctrl counter24:inst4|l[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.983 ns" { KEY_CHANGE KEY_CHANGE~combout inst16 inst16~clkctrl counter24:inst4|l[2] } { 0.000ns 0.000ns 1.990ns 2.562ns 1.191ns } { 0.000ns 0.924ns 0.650ns 0.000ns 0.666ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "20.063 ns" { KEY_CHANGE inst17~38 inst17~38clkctrl counter60:inst|cout inst15 inst15~clkctrl counter60:inst3|cout inst16 inst16~clkctrl counter24:inst4|l[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "20.063 ns" { KEY_CHANGE KEY_CHANGE~combout inst17~38 inst17~38clkctrl counter60:inst|cout inst15 inst15~clkctrl counter60:inst3|cout inst16 inst16~clkctrl counter24:inst4|l[1] } { 0.000ns 0.000ns 1.998ns 3.238ns 1.174ns 0.437ns 2.202ns 1.190ns 1.095ns 2.562ns 1.191ns } { 0.000ns 0.924ns 0.616ns 0.000ns 0.970ns 0.206ns 0.000ns 0.970ns 0.624ns 0.000ns 0.666ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "KEY_MODE register counter24:inst4\|l\[1\] register counter24:inst4\|l\[2\] 61.74 MHz 16.197 ns Internal " "Info: Clock \"KEY_MODE\" has Internal fmax of 61.74 MHz between source register \"counter24:inst4\|l\[1\]\" and destination register \"counter24:inst4\|l\[2\]\" (period= 16.197 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.643 ns + Longest register register " "Info: + Longest register to register delay is 3.643 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter24:inst4\|l\[1\] 1 REG LCFF_X42_Y14_N19 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X42_Y14_N19; Fanout = 8; REG Node = 'counter24:inst4\|l\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "" { counter24:inst4|l[1] } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "D:/quartus/myproject/clock/counter24.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.651 ns) 1.434 ns counter24:inst4\|LessThan~148 2 COMB LCCOMB_X42_Y14_N14 2 " "Info: 2: + IC(0.783 ns) + CELL(0.651 ns) = 1.434 ns; Loc. = LCCOMB_X42_Y14_N14; Fanout = 2; COMB Node = 'counter24:inst4\|LessThan~148'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "1.434 ns" { counter24:inst4|l[1] counter24:inst4|LessThan~148 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.370 ns) 2.198 ns counter24:inst4\|l\[3\]~841 3 COMB LCCOMB_X42_Y14_N24 4 " "Info: 3: + IC(0.394 ns) + CELL(0.370 ns) = 2.198 ns; Loc. = LCCOMB_X42_Y14_N24; Fanout = 4; COMB Node = 'counter24:inst4\|l\[3\]~841'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "0.764 ns" { counter24:inst4|LessThan~148 counter24:inst4|l[3]~841 } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "D:/quartus/myproject/clock/counter24.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.713 ns) + CELL(0.624 ns) 3.535 ns counter24:inst4\|l\[2\]~844 4 COMB LCCOMB_X42_Y14_N4 1 " "Info: 4: + IC(0.713 ns) + CELL(0.624 ns) = 3.535 ns; Loc. = LCCOMB_X42_Y14_N4; Fanout = 1; COMB Node = 'counter24:inst4\|l\[2\]~844'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "1.337 ns" { counter24:inst4|l[3]~841 counter24:inst4|l[2]~844 } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "D:/quartus/myproject/clock/counter24.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.643 ns counter24:inst4\|l\[2\] 5 REG LCFF_X42_Y14_N5 9 " "Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 3.643 ns; Loc. = LCFF_X42_Y14_N5; Fanout = 9; REG Node = 'counter24:inst4\|l\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "0.108 ns" { counter24:inst4|l[2]~844 counter24:inst4|l[2] } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "D:/quartus/myproject/clock/counter24.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.753 ns ( 48.12 % ) " "Info: Total cell delay = 1.753 ns ( 48.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.890 ns ( 51.88 % ) " "Info: Total interconnect delay = 1.890 ns ( 51.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "3.643 ns" { counter24:inst4|l[1] counter24:inst4|LessThan~148 counter24:inst4|l[3]~841 counter24:inst4|l[2]~844 counter24:inst4|l[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.643 ns" { counter24:inst4|l[1] counter24:inst4|LessThan~148 counter24:inst4|l[3]~841 counter24:inst4|l[2]~844 counter24:inst4|l[2] } { 0.000ns 0.783ns 0.394ns 0.713ns 0.000ns } { 0.000ns 0.651ns 0.370ns 0.624ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-12.290 ns - Smallest " "Info: - Smallest clock skew is -12.290 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "KEY_MODE destination 9.026 ns + Shortest register " "Info: + Shortest clock path from clock \"KEY_MODE\" to destination register is 9.026 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.924 ns) 0.924 ns KEY_MODE 1 CLK PIN_AB14 2 " "Info: 1: + IC(0.000 ns) + CELL(0.924 ns) = 0.924 ns; Loc. = PIN_AB14; Fanout = 2; CLK Node = 'KEY_MODE'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "" { KEY_MODE } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 64 8 176 80 "KEY_MODE" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.864 ns) + CELL(0.970 ns) 3.758 ns sel_mode:inst9\|mode\[1\] 2 REG LCFF_X43_Y12_N17 4 " "Info: 2: + IC(1.864 ns) + CELL(0.970 ns) = 3.758 ns; Loc. = LCFF_X43_Y12_N17; Fanout = 4; REG Node = 'sel_mode:inst9\|mode\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "2.834 ns" { KEY_MODE sel_mode:inst9|mode[1] } "NODE_NAME" } "" } } { "sel_mode.vhd" "" { Text "D:/quartus/myproject/clock/sel_mode.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.479 ns) + CELL(0.370 ns) 4.607 ns inst16 3 COMB LCCOMB_X43_Y12_N10 1 " "Info: 3: + IC(0.479 ns) + CELL(0.370 ns) = 4.607 ns; Loc. = LCCOMB_X43_Y12_N10; Fanout = 1; COMB Node = 'inst16'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "0.849 ns" { sel_mode:inst9|mode[1] inst16 } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 144 472 536 192 "inst16" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.562 ns) + CELL(0.000 ns) 7.169 ns inst16~clkctrl 4 COMB CLKCTRL_G5 6 " "Info: 4: + IC(2.562 ns) + CELL(0.000 ns) = 7.169 ns; Loc. = CLKCTRL_G5; Fanout = 6; COMB Node = 'inst16~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "2.562 ns" { inst16 inst16~clkctrl } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 144 472 536 192 "inst16" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.191 ns) + CELL(0.666 ns) 9.026 ns counter24:inst4\|l\[2\] 5 REG LCFF_X42_Y14_N5 9 " "Info: 5: + IC(1.191 ns) + CELL(0.666 ns) = 9.026 ns; Loc. = LCFF_X42_Y14_N5; Fanout = 9; REG Node = 'counter24:inst4\|l\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "1.857 ns" { inst16~clkctrl counter24:inst4|l[2] } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "D:/quartus/myproject/clock/counter24.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.930 ns ( 32.46 % ) " "Info: Total cell delay = 2.930 ns ( 32.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.096 ns ( 67.54 % ) " "Info: Total interconnect delay = 6.096 ns ( 67.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "9.026 ns" { KEY_MODE sel_mode:inst9|mode[1] inst16 inst16~clkctrl counter24:inst4|l[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "9.026 ns" { KEY_MODE KEY_MODE~combout sel_mode:inst9|mode[1] inst16 inst16~clkctrl counter24:inst4|l[2] } { 0.000ns 0.000ns 1.864ns 0.479ns 2.562ns 1.191ns } { 0.000ns 0.924ns 0.970ns 0.370ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "KEY_MODE source 21.316 ns - Longest register " "Info: - Longest clock path from clock \"KEY_MODE\" to source register is 21.316 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.924 ns) 0.924 ns KEY_MODE 1 CLK PIN_AB14 2 " "Info: 1: + IC(0.000 ns) + CELL(0.924 ns) = 0.924 ns; Loc. = PIN_AB14; Fanout = 2; CLK Node = 'KEY_MODE'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "" { KEY_MODE } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 64 8 176 80 "KEY_MODE" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.864 ns) + CELL(0.970 ns) 3.758 ns sel_mode:inst9\|mode\[1\] 2 REG LCFF_X43_Y12_N17 4 " "Info: 2: + IC(1.864 ns) + CELL(0.970 ns) = 3.758 ns; Loc. = LCFF_X43_Y12_N17; Fanout = 4; REG Node = 'sel_mode:inst9\|mode\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "2.834 ns" { KEY_MODE sel_mode:inst9|mode[1] } "NODE_NAME" } "" } } { "sel_mode.vhd" "" { Text "D:/quartus/myproject/clock/sel_mode.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.496 ns) + CELL(0.537 ns) 4.791 ns inst17~38 3 COMB LCCOMB_X43_Y12_N28 1 " "Info: 3: + I