clock.tan.qmsg

原创：基于VHDL语言编写的电子钟。采用模块化编写

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "9 " "Warning: Found 9 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "div_clock:inst6\|clk_1 " "Info: Detected ripple clock \"div_clock:inst6\|clk_1\" as buffer" {  } { { "div_clock.vhd" "" { Text "D:/quartus/myproject/clock/div_clock.vhd" 21 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "div_clock:inst6\|clk_1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "counter60:inst\|cout " "Info: Detected ripple clock \"counter60:inst\|cout\" as buffer" {  } { { "counter60.vhd" "" { Text "D:/quartus/myproject/clock/counter60.vhd" 9 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "counter60:inst\|cout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "inst17~38 " "Info: Detected gated clock \"inst17~38\" as buffer" {  } { { "clock.bdf" "" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 8 480 544 56 "inst17" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "inst17~38" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "sel_mode:inst9\|mode\[0\] " "Info: Detected ripple clock \"sel_mode:inst9\|mode\[0\]\" as buffer" {  } { { "sel_mode.vhd" "" { Text "D:/quartus/myproject/clock/sel_mode.vhd" 16 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sel_mode:inst9\|mode\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "sel_mode:inst9\|mode\[1\] " "Info: Detected ripple clock \"sel_mode:inst9\|mode\[1\]\" as buffer" {  } { { "sel_mode.vhd" "" { Text "D:/quartus/myproject/clock/sel_mode.vhd" 16 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sel_mode:inst9\|mode\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "counter60:inst3\|cout " "Info: Detected ripple clock \"counter60:inst3\|cout\" as buffer" {  } { { "counter60.vhd" "" { Text "D:/quartus/myproject/clock/counter60.vhd" 9 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "counter60:inst3\|cout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "inst15 " "Info: Detected gated clock \"inst15\" as buffer" {  } { { "clock.bdf" "" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 88 472 536 136 "inst15" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "inst15" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "inst16 " "Info: Detected gated clock \"inst16\" as buffer" {  } { { "clock.bdf" "" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 144 472 536 192 "inst16" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "inst16" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "div_clock:inst6\|clk_100 " "Info: Detected ripple clock \"div_clock:inst6\|clk_100\" as buffer" {  } { { "div_clock.vhd" "" { Text "D:/quartus/myproject/clock/div_clock.vhd" 21 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "div_clock:inst6\|clk_100" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register counter24:inst4\|h\[1\] register disp:inst2\|disp\[1\] 57.63 MHz 17.353 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 57.63 MHz between source register \"counter24:inst4\|h\[1\]\" and destination register \"disp:inst2\|disp\[1\]\" (period= 17.353 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.952 ns + Longest register register " "Info: + Longest register to register delay is 2.952 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter24:inst4\|h\[1\] 1 REG LCFF_X42_Y14_N3 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X42_Y14_N3; Fanout = 6; REG Node = 'counter24:inst4\|h\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "" { counter24:inst4|h[1] } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "D:/quartus/myproject/clock/counter24.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.461 ns) + CELL(0.366 ns) 1.827 ns disp:inst2\|Mux~691 2 COMB LCCOMB_X42_Y13_N28 1 " "Info: 2: + IC(1.461 ns) + CELL(0.366 ns) = 1.827 ns; Loc. = LCCOMB_X42_Y13_N28; Fanout = 1; COMB Node = 'disp:inst2\|Mux~691'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "1.827 ns" { counter24:inst4|h[1] disp:inst2|Mux~691 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.393 ns) + CELL(0.624 ns) 2.844 ns disp:inst2\|Mux~692 3 COMB LCCOMB_X42_Y13_N4 1 " "Info: 3: + IC(0.393 ns) + CELL(0.624 ns) = 2.844 ns; Loc. = LCCOMB_X42_Y13_N4; Fanout = 1; COMB Node = 'disp:inst2\|Mux~692'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "1.017 ns" { disp:inst2|Mux~691 disp:inst2|Mux~692 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.952 ns disp:inst2\|disp\[1\] 4 REG LCFF_X42_Y13_N5 7 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 2.952 ns; Loc. = LCFF_X42_Y13_N5; Fanout = 7; REG Node = 'disp:inst2\|disp\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "0.108 ns" { disp:inst2|Mux~692 disp:inst2|disp[1] } "NODE_NAME" } "" } } { "disp.vhd" "" { Text "D:/quartus/myproject/clock/disp.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.098 ns ( 37.20 % ) " "Info: Total cell delay = 1.098 ns ( 37.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.854 ns ( 62.80 % ) " "Info: Total interconnect delay = 1.854 ns ( 62.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "2.952 ns" { counter24:inst4|h[1] disp:inst2|Mux~691 disp:inst2|Mux~692 disp:inst2|disp[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.952 ns" { counter24:inst4|h[1] disp:inst2|Mux~691 disp:inst2|Mux~692 disp:inst2|disp[1] } { 0.000ns 1.461ns 0.393ns 0.000ns } { 0.000ns 0.366ns 0.624ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-14.137 ns - Smallest " "Info: - Smallest clock skew is -14.137 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 8.128 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 8.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.080 ns) 1.080 ns CLK 1 CLK PIN_B12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.080 ns) = 1.080 ns; Loc. = PIN_B12; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "" { CLK } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 16 8 176 32 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.219 ns CLK~clkctrl 2 COMB CLKCTRL_G10 25 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.219 ns; Loc. = CLKCTRL_G10; Fanout = 25; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "0.139 ns" { CLK CLK~clkctrl } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 16 8 176 32 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.162 ns) + CELL(0.970 ns) 3.351 ns div_clock:inst6\|clk_100 3 REG LCFF_X56_Y9_N25 2 " "Info: 3: + IC(1.162 ns) + CELL(0.970 ns) = 3.351 ns; Loc. = LCFF_X56_Y9_N25; Fanout = 2; REG Node = 'div_clock:inst6\|clk_100'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "2.132 ns" { CLK~clkctrl div_clock:inst6|clk_100 } "NODE_NAME" } "" } } { "div_clock.vhd" "" { Text "D:/quartus/myproject/clock/div_clock.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.925 ns) + CELL(0.000 ns) 6.276 ns div_clock:inst6\|clk_100~clkctrl 4 COMB CLKCTRL_G4 14 " "Info: 4: + IC(2.925 ns) + CELL(0.000 ns) = 6.276 ns; Loc. = CLKCTRL_G4; Fanout = 14; COMB Node = 'div_clock:inst6\|clk_100~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "2.925 ns" { div_clock:inst6|clk_100 div_clock:inst6|clk_100~clkctrl } "NODE_NAME" } "" } } { "div_clock.vhd" "" { Text "D:/quartus/myproject/clock/div_clock.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.186 ns) + CELL(0.666 ns) 8.128 ns disp:inst2\|disp\[1\] 5 REG LCFF_X42_Y13_N5 7 " "Info: 5: + IC(1.186 ns) + CELL(0.666 ns) = 8.128 ns; Loc. = LCFF_X42_Y13_N5; Fanout = 7; REG Node = 'disp:inst2\|disp\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "1.852 ns" { div_clock:inst6|clk_100~clkctrl disp:inst2|disp[1] } "NODE_NAME" } "" } } { "disp.vhd" "" { Text "D:/quartus/myproject/clock/disp.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.716 ns ( 33.42 % ) " "Info: Total cell delay = 2.716 ns ( 33.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.412 ns ( 66.58 % ) " "Info: Total interconnect delay = 5.412 ns ( 66.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "8.128 ns" { CLK CLK~clkctrl div_clock:inst6|clk_100 div_clock:inst6|clk_100~clkctrl disp:inst2|disp[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.128 ns" { CLK CLK~combout CLK~clkctrl div_clock:inst6|clk_100 div_clock:inst6|clk_100~clkctrl disp:inst2|disp[1] } { 0.000ns 0.000ns 0.139ns 1.162ns 2.925ns 1.186ns } { 0.000ns 1.080ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 22.265 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 22.265 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.080 ns) 1.080 ns CLK 1 CLK PIN_B12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.080 ns) = 1.080 ns; Loc. = PIN_B12; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "" { CLK } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 16 8 176 32 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.219 ns CLK~clkctrl 2 COMB CLKCTRL_G10 25 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.219 ns; Loc. = CLKCTRL_G10; Fanout = 25; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "0.139 ns" { CLK CLK~clkctrl } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 16 8 176 32 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.161 ns) + CELL(0.970 ns) 3.350 ns div_clock:inst6\|clk_1 3 REG LCFF_X55_Y9_N29 2 " "Info: 3: + IC(1.161 ns) + CELL(0.970 ns) = 3.350 ns; Loc. = LCFF_X55_Y9_N29; Fanout = 2; REG Node = 'div_clock:inst6\|clk_1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "2.131 ns" { CLK~clkctrl div_clock:inst6|clk_1 } "NODE_NAME" } "" } } { "div_clock.vhd" "" { Text "D:/quartus/myproject/clock/div_clock.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.184 ns) + CELL(0.206 ns) 5.740 ns inst17~38 4 COMB LCCOMB_X43_Y12_N28 1 " "Info: 4: + IC(2.184 ns) + CELL(0.206 ns) = 5.740 ns; Loc. = LCCOMB_X43_Y12_N28; Fanout = 1; COMB Node = 'inst17~38'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "2.390 ns" { div_clock:inst6|clk_1 inst17~38 } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 8 480 544 56 "inst17" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.238 ns) + CELL(0.000 ns) 8.978 ns inst17~38clkctrl 5 COMB CLKCTRL_G2 8 " "Info: 5: + IC(3.238 ns) + CELL(0.000 ns) = 8.978 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'inst17~38clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "3.238 ns" { inst17~38 inst17~38clkctrl } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 8 480 544 56 "inst17" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.174 ns) + CELL(0.970 ns) 11.122 ns counter60:inst\|cout 6 REG LCFF_X43_Y12_N3 2 " "Info: 6: + IC(1.174 ns) + CELL(0.970 ns) = 11.122 ns; Loc. = LCFF_X43_Y12_N3; Fanout = 2; REG Node = 'counter60:inst\|cout'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "2.144 ns" { inst17~38clkctrl counter60:inst|cout } "NODE_NAME" } "" } } { "counter60.vhd" "" { Text "D:/quartus/myproject/clock/counter60.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.437 ns) + CELL(0.206 ns) 11.765 ns inst15 7 COMB LCCOMB_X43_Y12_N4 1 " "Info: 7: + IC(0.437 ns) + CELL(0.206 ns) = 11.765 ns; Loc. = LCCOMB_X43_Y12_N4; Fanout = 1; COMB Node = 'inst15'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "0.643 ns" { counter60:inst|cout inst15 } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 88 472 536 136 "inst15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.202 ns) + CELL(0.000 ns) 13.967 ns inst15~clkctrl 8 COMB CLKCTRL_G6 8 " "Info: 8: + IC(2.202 ns) + CELL(0.000 ns) = 13.967 ns; Loc. = CLKCTRL_G6; Fanout = 8; COMB Node = 'inst15~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "2.202 ns" { inst15 inst15~clkctrl } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 88 472 536 136 "inst15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.190 ns) + CELL(0.970 ns) 16.127 ns counter60:inst3\|cout 9 REG LCFF_X43_Y14_N27 3 " "Info: 9: + IC(1.190 ns) + CELL(0.970 ns) = 16.127 ns; Loc. = LCFF_X43_Y14_N27; Fanout = 3; REG Node = 'counter60:inst3\|cout'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "2.160 ns" { inst15~clkctrl counter60:inst3|cout } "NODE_NAME" } "" } } { "counter60.vhd" "" { Text "D:/quartus/myproject/clock/counter60.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.095 ns) + CELL(0.624 ns) 17.846 ns inst16 10 COMB LCCOMB_X43_Y12_N10 1 " "Info: 10: + IC(1.095 ns) + CELL(0.624 ns) = 17.846 ns; Loc. = LCCOMB_X43_Y12_N10; Fanout = 1; COMB Node = 'inst16'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "1.719 ns" { counter60:inst3|cout inst16 } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 144 472 536 192 "inst16" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.562 ns) + CELL(0.000 ns) 20.408 ns inst16~clkctrl 11 COMB CLKCTRL_G5 6 " "Info: 11: + IC(2.562 ns) + CELL(0.000 ns) = 20.408 ns; Loc. = CLKCTRL_G5; Fanout = 6; COMB Node = 'inst16~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "2.562 ns" { inst16 inst16~clkctrl } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "D:/quartus/myproject/clock/clock.bdf" { { 144 472 536 192 "inst16" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.191 ns) + CELL(0.666 ns) 22.265 ns counter24:inst4\|h\[1\] 12 REG LCFF_X42_Y14_N3 6 " "Info: 12: + IC(1.191 ns) + CELL(0.666 ns) = 22.265 ns; Loc. = LCFF_X42_Y14_N3; Fanout = 6; REG Node = 'counter24:inst4\|h\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "1.857 ns" { inst16~clkctrl counter24:inst4|h[1] } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "D:/quartus/myproject/clock/counter24.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.692 ns ( 25.56 % ) " "Info: Total cell delay = 5.692 ns ( 25.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "16.573 ns ( 74.44 % ) " "Info: Total interconnect delay = 16.573 ns ( 74.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "22.265 ns" { CLK CLK~clkctrl div_clock:inst6|clk_1 inst17~38 inst17~38clkctrl counter60:inst|cout inst15 inst15~clkctrl counter60:inst3|cout inst16 inst16~clkctrl counter24:inst4|h[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "22.265 ns" { CLK CLK~combout CLK~clkctrl div_clock:inst6|clk_1 inst17~38 inst17~38clkctrl counter60:inst|cout inst15 inst15~clkctrl counter60:inst3|cout inst16 inst16~clkctrl counter24:inst4|h[1] } { 0.000ns 0.000ns 0.139ns 1.161ns 2.184ns 3.238ns 1.174ns 0.437ns 2.202ns 1.190ns 1.095ns 2.562ns 1.191ns } { 0.000ns 1.080ns 0.000ns 0.970ns 0.206ns 0.000ns 0.970ns 0.206ns 0.000ns 0.970ns 0.624ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "8.128 ns" { CLK CLK~clkctrl div_clock:inst6|clk_100 div_clock:inst6|clk_100~clkctrl disp:inst2|disp[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.128 ns" { CLK CLK~combout CLK~clkctrl div_clock:inst6|clk_100 div_clock:inst6|clk_100~clkctrl disp:inst2|disp[1] } { 0.000ns 0.000ns 0.139ns 1.162ns 2.925ns 1.186ns } { 0.000ns 1.080ns 0.000ns 0.970ns 0.000ns 0.666ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "22.265 ns" { CLK CLK~clkctrl div_clock:inst6|clk_1 inst17~38 inst17~38clkctrl counter60:inst|cout inst15 inst15~clkctrl counter60:inst3|cout inst16 inst16~clkctrl counter24:inst4|h[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "22.265 ns" { CLK CLK~combout CLK~clkctrl div_clock:inst6|clk_1 inst17~38 inst17~38clkctrl counter60:inst|cout inst15 inst15~clkctrl counter60:inst3|cout inst16 inst16~clkctrl counter24:inst4|h[1] } { 0.000ns 0.000ns 0.139ns 1.161ns 2.184ns 3.238ns 1.174ns 0.437ns 2.202ns 1.190ns 1.095ns 2.562ns 1.191ns } { 0.000ns 1.080ns 0.000ns 0.970ns 0.206ns 0.000ns 0.970ns 0.206ns 0.000ns 0.970ns 0.624ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "counter24.vhd" "" { Text "D:/quartus/myproject/clock/counter24.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "disp.vhd" "" { Text "D:/quartus/myproject/clock/disp.vhd" 31 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "2.952 ns" { counter24:inst4|h[1] disp:inst2|Mux~691 disp:inst2|Mux~692 disp:inst2|disp[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.952 ns" { counter24:inst4|h[1] disp:inst2|Mux~691 disp:inst2|Mux~692 disp:inst2|disp[1] } { 0.000ns 1.461ns 0.393ns 0.000ns } { 0.000ns 0.366ns 0.624ns 0.108ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "8.128 ns" { CLK CLK~clkctrl div_clock:inst6|clk_100 div_clock:inst6|clk_100~clkctrl disp:inst2|disp[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.128 ns" { CLK CLK~combout CLK~clkctrl div_clock:inst6|clk_100 div_clock:inst6|clk_100~clkctrl disp:inst2|disp[1] } { 0.000ns 0.000ns 0.139ns 1.162ns 2.925ns 1.186ns } { 0.000ns 1.080ns 0.000ns 0.970ns 0.000ns 0.666ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "22.265 ns" { CLK CLK~clkctrl div_clock:inst6|clk_1 inst17~38 inst17~38clkctrl counter60:inst|cout inst15 inst15~clkctrl counter60:inst3|cout inst16 inst16~clkctrl counter24:inst4|h[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "22.265 ns" { CLK CLK~combout CLK~clkctrl div_clock:inst6|clk_1 inst17~38 inst17~38clkctrl counter60:inst|cout inst15 inst15~clkctrl counter60:inst3|cout inst16 inst16~clkctrl counter24:inst4|h[1] } { 0.000ns 0.000ns 0.139ns 1.161ns 2.184ns 3.238ns 1.174ns 0.437ns 2.202ns 1.190ns 1.095ns 2.562ns 1.191ns } { 0.000ns 1.080ns 0.000ns 0.970ns 0.206ns 0.000ns 0.970ns 0.206ns 0.000ns 0.970ns 0.624ns 0.000ns 0.666ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}