clock.fit.qmsg

原创：基于VHDL语言编写的电子钟。采用模块化编写

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0 0 "Finished register packing" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.511 ns register register " "Info: Estimated most critical path is register to register delay of 2.511 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter24:inst4\|l\[1\] 1 REG LAB_X42_Y14 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X42_Y14; Fanout = 8; REG Node = 'counter24:inst4\|l\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "" { counter24:inst4|l[1] } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "D:/quartus/myproject/clock/counter24.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.940 ns) + CELL(0.651 ns) 1.591 ns disp:inst2\|Mux~691 2 COMB LAB_X42_Y13 1 " "Info: 2: + IC(0.940 ns) + CELL(0.651 ns) = 1.591 ns; Loc. = LAB_X42_Y13; Fanout = 1; COMB Node = 'disp:inst2\|Mux~691'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "1.591 ns" { counter24:inst4|l[1] disp:inst2|Mux~691 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.188 ns) + CELL(0.624 ns) 2.403 ns disp:inst2\|Mux~692 3 COMB LAB_X42_Y13 1 " "Info: 3: + IC(0.188 ns) + CELL(0.624 ns) = 2.403 ns; Loc. = LAB_X42_Y13; Fanout = 1; COMB Node = 'disp:inst2\|Mux~692'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "0.812 ns" { disp:inst2|Mux~691 disp:inst2|Mux~692 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.511 ns disp:inst2\|disp\[1\] 4 REG LAB_X42_Y13 7 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 2.511 ns; Loc. = LAB_X42_Y13; Fanout = 7; REG Node = 'disp:inst2\|disp\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "0.108 ns" { disp:inst2|Mux~692 disp:inst2|disp[1] } "NODE_NAME" } "" } } { "disp.vhd" "" { Text "D:/quartus/myproject/clock/disp.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.383 ns ( 55.08 % ) " "Info: Total cell delay = 1.383 ns ( 55.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.128 ns ( 44.92 % ) " "Info: Total interconnect delay = 1.128 ns ( 44.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "D:/quartus/myproject/clock/db/clock.quartus_db" { Floorplan "D:/quartus/myproject/clock/" "" "2.511 ns" { counter24:inst4|l[1] disp:inst2|Mux~691 disp:inst2|Mux~692 disp:inst2|disp[1] } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:04 " "Info: Fitter routing operations ending: elapsed time is 00:00:04" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Warning" "WDAT_PRELIMINARY_TIMING" "EP2C35F484C8 " "Warning: Timing characteristics of device EP2C35F484C8 are preliminary" {  } {  } 0 0 "Timing characteristics of device %1!s! are preliminary" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "14 " "Warning: Found 14 output pins without output pin load capacitance assignment" { { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "dp 0 " "Warning: Pin \"dp\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "disp\[6\] 0 " "Warning: Pin \"disp\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "disp\[5\] 0 " "Warning: Pin \"disp\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "disp\[4\] 0 " "Warning: Pin \"disp\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "disp\[3\] 0 " "Warning: Pin \"disp\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "disp\[2\] 0 " "Warning: Pin \"disp\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "disp\[1\] 0 " "Warning: Pin \"disp\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "disp\[0\] 0 " "Warning: Pin \"disp\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "sel\[5\] 0 " "Warning: Pin \"sel\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "sel\[4\] 0 " "Warning: Pin \"sel\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "sel\[3\] 0 " "Warning: Pin \"sel\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "sel\[2\] 0 " "Warning: Pin \"sel\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "sel\[1\] 0 " "Warning: Pin \"sel\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "sel\[0\] 0 " "Warning: Pin \"sel\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 16 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 11 22:55:47 2008 " "Info: Processing ended: Tue Nov 11 22:55:47 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:53 " "Info: Elapsed time: 00:00:53" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}