clock.sim.rpt

原创：基于VHDL语言编写的电子钟。采用模块化编写

; |clock|MINH[3]                         ; |clock|MINH[3]                         ; padio            ;
; |clock|MINH[2]                         ; |clock|MINH[2]                         ; padio            ;
; |clock|MINH[1]                         ; |clock|MINH[1]                         ; padio            ;
; |clock|MINH[0]                         ; |clock|MINH[0]                         ; padio            ;
; |clock|MINL[6]                         ; |clock|MINL[6]                         ; padio            ;
; |clock|MINL[5]                         ; |clock|MINL[5]                         ; padio            ;
; |clock|MINL[4]                         ; |clock|MINL[4]                         ; padio            ;
; |clock|MINL[3]                         ; |clock|MINL[3]                         ; padio            ;
; |clock|MINL[2]                         ; |clock|MINL[2]                         ; padio            ;
; |clock|MINL[1]                         ; |clock|MINL[1]                         ; padio            ;
; |clock|MINL[0]                         ; |clock|MINL[0]                         ; padio            ;
; |clock|SECH[6]                         ; |clock|SECH[6]                         ; padio            ;
; |clock|SECH[5]                         ; |clock|SECH[5]                         ; padio            ;
; |clock|SECH[4]                         ; |clock|SECH[4]                         ; padio            ;
; |clock|SECH[3]                         ; |clock|SECH[3]                         ; padio            ;
; |clock|SECH[2]                         ; |clock|SECH[2]                         ; padio            ;
; |clock|SECH[1]                         ; |clock|SECH[1]                         ; padio            ;
; |clock|SECH[0]                         ; |clock|SECH[0]                         ; padio            ;
; |clock|SECL[6]                         ; |clock|SECL[6]                         ; padio            ;
; |clock|SECL[5]                         ; |clock|SECL[5]                         ; padio            ;
; |clock|SECL[4]                         ; |clock|SECL[4]                         ; padio            ;
; |clock|SECL[3]                         ; |clock|SECL[3]                         ; padio            ;
; |clock|SECL[2]                         ; |clock|SECL[2]                         ; padio            ;
; |clock|SECL[1]                         ; |clock|SECL[1]                         ; padio            ;
; |clock|SECL[0]                         ; |clock|SECL[0]                         ; padio            ;
+----------------------------------------+----------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+----------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                           ;
+----------------------------------------+----------------------------------------+------------------+
; Node Name                              ; Output Port Name                       ; Output Port Type ;
+----------------------------------------+----------------------------------------+------------------+
; |clock|counter24:inst4|h[0]            ; |clock|counter24:inst4|h[0]            ; regout           ;
; |clock|bcd_decoder:inst14|LED7S[5]~89  ; |clock|bcd_decoder:inst14|LED7S[5]~89  ; combout          ;
; |clock|bcd_decoder:inst14|LED7S[3]~90  ; |clock|bcd_decoder:inst14|LED7S[3]~90  ; combout          ;
; |clock|bcd_decoder:inst14|LED7S[2]~91  ; |clock|bcd_decoder:inst14|LED7S[2]~91  ; combout          ;
; |clock|counter24:inst4|l[3]            ; |clock|counter24:inst4|l[3]            ; regout           ;
; |clock|bcd_decoder:inst13|LED7S[6]~191 ; |clock|bcd_decoder:inst13|LED7S[6]~191 ; combout          ;
; |clock|bcd_decoder:inst13|LED7S[2]~195 ; |clock|bcd_decoder:inst13|LED7S[2]~195 ; combout          ;
; |clock|bcd_decoder:inst13|LED7S[1]~196 ; |clock|bcd_decoder:inst13|LED7S[1]~196 ; combout          ;
; |clock|counter24:inst4|h[1]~399        ; |clock|counter24:inst4|h[1]~399        ; combout          ;
; |clock|counter24:inst4|h[1]~400        ; |clock|counter24:inst4|h[1]~400        ; combout          ;
; |clock|rtl~85                          ; |clock|rtl~85                          ; combout          ;
; |clock|counter24:inst4|l[2]~814        ; |clock|counter24:inst4|l[2]~814        ; combout          ;
; |clock|counter24:inst4|h[0]~402        ; |clock|counter24:inst4|h[0]~402        ; combout          ;
; |clock|counter24:inst4|l[1]~815        ; |clock|counter24:inst4|l[1]~815        ; combout          ;
; |clock|counter24:inst4|l[1]~816        ; |clock|counter24:inst4|l[1]~816        ; combout          ;
; |clock|counter24:inst4|l[1]~817        ; |clock|counter24:inst4|l[1]~817        ; combout          ;
; |clock|counter24:inst4|l[1]~818        ; |clock|counter24:inst4|l[1]~818        ; combout          ;
; |clock|counter24:inst4|LessThan~148    ; |clock|counter24:inst4|LessThan~148    ; combout          ;
; |clock|counter24:inst4|add~146         ; |clock|counter24:inst4|add~146         ; combout          ;
; |clock|counter60:inst|l[0]~617         ; |clock|counter60:inst|l[0]~617         ; combout          ;
; |clock|sel_mode:inst19|Mux~79          ; |clock|sel_mode:inst19|Mux~79          ; combout          ;
; |clock|sel_mode:inst19|Mux~80          ; |clock|sel_mode:inst19|Mux~80          ; combout          ;
; |clock|sel_mode:inst19|Mux~80          ; |clock|sel_mode:inst19|mode[1]         ; regout           ;
; |clock|sel_mode:inst19|Mux~81          ; |clock|sel_mode:inst19|Mux~81          ; combout          ;
; |clock|sel_mode:inst19|sel_hour        ; |clock|sel_mode:inst19|sel_hour        ; combout          ;
; |clock|sel_mode:inst19|sel_min         ; |clock|sel_mode:inst19|sel_min         ; combout          ;
; |clock|sel_mode:inst19|sel_sec         ; |clock|sel_mode:inst19|sel_sec         ; combout          ;
; |clock|RESET                           ; |clock|RESET                           ; combout          ;
; |clock|KEY_CHANGE                      ; |clock|KEY_CHANGE                      ; combout          ;
; |clock|KEY_MODE                        ; |clock|KEY_MODE                        ; combout          ;
; |clock|HOURH[6]                        ; |clock|HOURH[6]                        ; padio            ;
; |clock|HOURH[5]                        ; |clock|HOURH[5]                        ; padio            ;
; |clock|HOURH[4]                        ; |clock|HOURH[4]                        ; padio            ;
; |clock|HOURH[3]                        ; |clock|HOURH[3]                        ; padio            ;
; |clock|HOURH[2]                        ; |clock|HOURH[2]                        ; padio            ;
; |clock|HOURH[1]                        ; |clock|HOURH[1]                        ; padio            ;
; |clock|HOURH[0]                        ; |clock|HOURH[0]                        ; padio            ;
; |clock|HOURL[6]                        ; |clock|HOURL[6]                        ; padio            ;
; |clock|HOURL[5]                        ; |clock|HOURL[5]                        ; padio            ;
; |clock|HOURL[4]                        ; |clock|HOURL[4]                        ; padio            ;
; |clock|HOURL[3]                        ; |clock|HOURL[3]                        ; padio            ;
; |clock|HOURL[2]                        ; |clock|HOURL[2]                        ; padio            ;
; |clock|HOURL[1]                        ; |clock|HOURL[1]                        ; padio            ;
; |clock|HOURL[0]                        ; |clock|HOURL[0]                        ; padio            ;
; |clock|~STRATIX_FITTER_CREATED_GND~I   ; |clock|~STRATIX_FITTER_CREATED_GND~I   ; combout          ;
+----------------------------------------+----------------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+----------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                                           ;
+----------------------------------------+----------------------------------------+------------------+
; Node Name                              ; Output Port Name                       ; Output Port Type ;
+----------------------------------------+----------------------------------------+------------------+
; |clock|counter24:inst4|h[0]            ; |clock|counter24:inst4|h[0]            ; regout           ;
; |clock|bcd_decoder:inst14|LED7S[5]~89  ; |clock|bcd_decoder:inst14|LED7S[5]~89  ; combout          ;
; |clock|bcd_decoder:inst14|LED7S[3]~90  ; |clock|bcd_decoder:inst14|LED7S[3]~90  ; combout          ;
; |clock|bcd_decoder:inst14|LED7S[2]~91  ; |clock|bcd_decoder:inst14|LED7S[2]~91  ; combout          ;
; |clock|counter24:inst4|l[3]            ; |clock|counter24:inst4|l[3]            ; regout           ;
; |clock|bcd_decoder:inst13|LED7S[6]~191 ; |clock|bcd_decoder:inst13|LED7S[6]~191 ; combout          ;
; |clock|bcd_decoder:inst13|LED7S[5]~192 ; |clock|bcd_decoder:inst13|LED7S[5]~192 ; combout          ;
; |clock|bcd_decoder:inst13|LED7S[4]~193 ; |clock|bcd_decoder:inst13|LED7S[4]~193 ; combout          ;
; |clock|bcd_decoder:inst13|LED7S[3]~194 ; |clock|bcd_decoder:inst13|LED7S[3]~194 ; combout          ;
; |clock|bcd_decoder:inst13|LED7S[2]~195 ; |clock|bcd_decoder:inst13|LED7S[2]~195 ; combout          ;
; |clock|bcd_decoder:inst13|LED7S[1]~196 ; |clock|bcd_decoder:inst13|LED7S[1]~196 ; combout          ;
; |clock|bcd_decoder:inst13|LED7S[0]~197 ; |clock|bcd_decoder:inst13|LED7S[0]~197 ; combout          ;
; |clock|counter24:inst4|h[1]~399        ; |clock|counter24:inst4|h[1]~399        ; combout          ;
; |clock|counter24:inst4|h[1]~400        ; |clock|counter24:inst4|h[1]~400        ; combout          ;
; |clock|rtl~85                          ; |clock|rtl~85                          ; combout          ;
; |clock|counter24:inst4|h[0]~402        ; |clock|counter24:inst4|h[0]~402        ; combout          ;
; |clock|counter24:inst4|l[1]~815        ; |clock|counter24:inst4|l[1]~815        ; combout          ;
; |clock|counter24:inst4|l[1]~816        ; |clock|counter24:inst4|l[1]~816        ; combout          ;
; |clock|counter24:inst4|l[1]~817        ; |clock|counter24:inst4|l[1]~817        ; combout          ;
; |clock|counter24:inst4|l[1]~818        ; |clock|counter24:inst4|l[1]~818        ; combout          ;
; |clock|counter24:inst4|LessThan~148    ; |clock|counter24:inst4|LessThan~148    ; combout          ;
; |clock|counter24:inst4|add~146         ; |clock|counter24:inst4|add~146         ; combout          ;
; |clock|counter60:inst|l[0]~617         ; |clock|counter60:inst|l[0]~617         ; combout          ;
; |clock|sel_mode:inst19|Mux~79          ; |clock|sel_mode:inst19|Mux~79          ; combout          ;
; |clock|sel_mode:inst19|Mux~80          ; |clock|sel_mode:inst19|Mux~80          ; combout          ;
; |clock|sel_mode:inst19|Mux~80          ; |clock|sel_mode:inst19|mode[1]         ; regout           ;
; |clock|sel_mode:inst19|Mux~81          ; |clock|sel_mode:inst19|Mux~81          ; combout          ;
; |clock|sel_mode:inst19|sel_hour        ; |clock|sel_mode:inst19|sel_hour        ; combout          ;
; |clock|sel_mode:inst19|sel_min         ; |clock|sel_mode:inst19|sel_min         ; combout          ;
; |clock|sel_mode:inst19|sel_sec         ; |clock|sel_mode:inst19|sel_sec         ; combout          ;
; |clock|RESET                           ; |clock|RESET                           ; combout          ;
; |clock|KEY_CHANGE                      ; |clock|KEY_CHANGE                      ; combout          ;
; |clock|KEY_MODE                        ; |clock|KEY_MODE                        ; combout          ;
; |clock|HOURH[6]                        ; |clock|HOURH[6]                        ; padio            ;
; |clock|HOURH[5]                        ; |clock|HOURH[5]                        ; padio            ;
; |clock|HOURH[4]                        ; |clock|HOURH[4]                        ; padio            ;
; |clock|HOURH[3]                        ; |clock|HOURH[3]                        ; padio            ;
; |clock|HOURH[2]                        ; |clock|HOURH[2]                        ; padio            ;
; |clock|HOURH[1]                        ; |clock|HOURH[1]                        ; padio            ;
; |clock|HOURH[0]                        ; |clock|HOURH[0]                        ; padio            ;
; |clock|HOURL[6]                        ; |clock|HOURL[6]                        ; padio            ;
; |clock|HOURL[2]                        ; |clock|HOURL[2]                        ; padio            ;
; |clock|HOURL[1]                        ; |clock|HOURL[1]                        ; padio            ;
; |clock|~STRATIX_FITTER_CREATED_GND~I   ; |clock|~STRATIX_FITTER_CREATED_GND~I   ; combout          ;
+----------------------------------------+----------------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Sat Nov 08 22:05:47 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off clock -c clock
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      62.88 %
Info: Number of transitions in simulation is 105302
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Processing ended: Sat Nov 08 22:05:51 2008
    Info: Elapsed time: 00:00:08