sel_mode.vhd

原创：基于VHDL语言编写的电子钟。采用模块化编写

library ieee;
use ieee.std_logic_1164.all;

entity sel_mode is
port(
	 rst,clk,key_clk,key_mode:in std_logic;
	 qclk,sel_sec,sel_min,sel_hour:out std_logic
);
end entity sel_mode;

architecture beh of sel_mode is
signal mode:integer range 0 to 3;
begin
P1:	process(key_mode,rst)
	begin
		if(rst='0')then
			mode<=0;
		elsif(key_mode' event and key_mode='1')then
			mode<=mode+1;
			if(mode=4)then
			mode<=0;
			end if;
		end if;
	end process P1;
P2:process(mode,key_clk,clk)
	begin
		case mode is
		when 0=>qclk<=clk;sel_sec<='0';sel_min<='0';sel_hour<='0';
		when 1=>sel_sec<=key_clk;qclk<='0';sel_min<='0';sel_hour<='0';
		when 2=>sel_min<=key_clk;qclk<='0';sel_sec<='0';sel_hour<='0';
		when 3=>sel_hour<=key_clk;qclk<='0';sel_min<='0';sel_sec<='0';
		when others=> qclk<=null;
		end case;
	end process P2;
end architecture beh;