clock.vhd

原创：基于VHDL语言编写的电子钟。采用模块化编写

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 5.1 Build 176 10/26/2005 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY clock IS 
	port
	(
		RESET :  IN  STD_LOGIC;
		KEY_CHANGE :  IN  STD_LOGIC;
		KEY_MODE :  IN  STD_LOGIC;
		CLK :  IN  STD_LOGIC;
		dp :  OUT  STD_LOGIC;
		disp :  OUT  STD_LOGIC_VECTOR(6 downto 0);
		sel :  OUT  STD_LOGIC_VECTOR(5 downto 0)
	);
END clock;

ARCHITECTURE bdf_type OF clock IS 

component counter60
	PORT(clk : IN STD_LOGIC;
		 clr : IN STD_LOGIC;
		 cout : OUT STD_LOGIC;
		 high : OUT STD_LOGIC_VECTOR(3 downto 0);
		 low : OUT STD_LOGIC_VECTOR(3 downto 0)
	);
end component;

component disp
	PORT(clk1 : IN STD_LOGIC;
		 rst : IN STD_LOGIC;
		 hourh : IN STD_LOGIC_VECTOR(3 downto 0);
		 hourl : IN STD_LOGIC_VECTOR(3 downto 0);
		 minh : IN STD_LOGIC_VECTOR(3 downto 0);
		 minl : IN STD_LOGIC_VECTOR(3 downto 0);
		 sech : IN STD_LOGIC_VECTOR(3 downto 0);
		 secl : IN STD_LOGIC_VECTOR(3 downto 0);
		 dp : OUT STD_LOGIC;
		 disp : OUT STD_LOGIC_VECTOR(3 downto 0);
		 sel : OUT STD_LOGIC_VECTOR(5 downto 0)
	);
end component;

component counter24
	PORT(clk : IN STD_LOGIC;
		 clr : IN STD_LOGIC;
		 cout : OUT STD_LOGIC;
		 high : OUT STD_LOGIC_VECTOR(3 downto 0);
		 low : OUT STD_LOGIC_VECTOR(3 downto 0)
	);
end component;

component bcd_decoder
	PORT(ina : IN STD_LOGIC_VECTOR(3 downto 0);
		 LED7S : OUT STD_LOGIC_VECTOR(6 downto 0)
	);
end component;

component div_clock
	PORT(clk : IN STD_LOGIC;
		 clk_1hz : OUT STD_LOGIC;
		 clk_100hz : OUT STD_LOGIC
	);
end component;

component sel_mode
	PORT(rst : IN STD_LOGIC;
		 clk : IN STD_LOGIC;
		 key_clk : IN STD_LOGIC;
		 key_mode : IN STD_LOGIC;
		 qclk : OUT STD_LOGIC;
		 sel_sec : OUT STD_LOGIC;
		 sel_min : OUT STD_LOGIC;
		 sel_hour : OUT STD_LOGIC
	);
end component;

signal	SYNTHESIZED_WIRE_0 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_1 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_2 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_3 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_4 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_5 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_6 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_7 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_8 :  STD_LOGIC_VECTOR(3 downto 0);
signal	SYNTHESIZED_WIRE_9 :  STD_LOGIC_VECTOR(3 downto 0);
signal	SYNTHESIZED_WIRE_10 :  STD_LOGIC_VECTOR(3 downto 0);
signal	SYNTHESIZED_WIRE_11 :  STD_LOGIC_VECTOR(3 downto 0);
signal	SYNTHESIZED_WIRE_12 :  STD_LOGIC_VECTOR(3 downto 0);
signal	SYNTHESIZED_WIRE_13 :  STD_LOGIC_VECTOR(3 downto 0);
signal	SYNTHESIZED_WIRE_14 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_15 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_16 :  STD_LOGIC_VECTOR(3 downto 0);
signal	SYNTHESIZED_WIRE_17 :  STD_LOGIC;


BEGIN 



b2v_inst : counter60
PORT MAP(clk => SYNTHESIZED_WIRE_0,
		 clr => RESET,
		 cout => SYNTHESIZED_WIRE_2,
		 high => SYNTHESIZED_WIRE_12,
		 low => SYNTHESIZED_WIRE_13);

SYNTHESIZED_WIRE_14 <= SYNTHESIZED_WIRE_1 OR SYNTHESIZED_WIRE_2;

SYNTHESIZED_WIRE_15 <= SYNTHESIZED_WIRE_3 OR SYNTHESIZED_WIRE_4;

SYNTHESIZED_WIRE_0 <= SYNTHESIZED_WIRE_5 OR SYNTHESIZED_WIRE_6;

b2v_inst2 : disp
PORT MAP(clk1 => SYNTHESIZED_WIRE_7,
		 rst => RESET,
		 hourh => SYNTHESIZED_WIRE_8,
		 hourl => SYNTHESIZED_WIRE_9,
		 minh => SYNTHESIZED_WIRE_10,
		 minl => SYNTHESIZED_WIRE_11,
		 sech => SYNTHESIZED_WIRE_12,
		 secl => SYNTHESIZED_WIRE_13,
		 dp => dp,
		 disp => SYNTHESIZED_WIRE_16,
		 sel => sel);

b2v_inst3 : counter60
PORT MAP(clk => SYNTHESIZED_WIRE_14,
		 clr => RESET,
		 cout => SYNTHESIZED_WIRE_3,
		 high => SYNTHESIZED_WIRE_10,
		 low => SYNTHESIZED_WIRE_11);

b2v_inst4 : counter24
PORT MAP(clk => SYNTHESIZED_WIRE_15,
		 clr => RESET,
		 high => SYNTHESIZED_WIRE_8,
		 low => SYNTHESIZED_WIRE_9);

b2v_inst5 : bcd_decoder
PORT MAP(ina => SYNTHESIZED_WIRE_16,
		 LED7S => disp);

b2v_inst6 : div_clock
PORT MAP(clk => CLK,
		 clk_1hz => SYNTHESIZED_WIRE_17,
		 clk_100hz => SYNTHESIZED_WIRE_7);

b2v_inst9 : sel_mode
PORT MAP(rst => RESET,
		 clk => SYNTHESIZED_WIRE_17,
		 key_clk => KEY_CHANGE,
		 key_mode => KEY_MODE,
		 qclk => SYNTHESIZED_WIRE_6,
		 sel_sec => SYNTHESIZED_WIRE_5,
		 sel_min => SYNTHESIZED_WIRE_1,
		 sel_hour => SYNTHESIZED_WIRE_4);

END;