clock.map.eqn

原创：基于VHDL语言编写的电子钟。采用模块化编写

--D1L4 is counter24:inst4|h[0]~333
D1L4 = D1_h[0] $ (!D1_h[1] & !D1L21 & A1L23);


--B1L13 is counter60:inst3|h[1]~703
B1L13 = !B1_h[0] & !B1_h[1] # !B1_h[2];


--B1L14 is counter60:inst3|h[1]~704
B1L14 = B1L26 & B1_h[0] & B1L10 # !B1L26 & (B1_h[2]);


--B1L15 is counter60:inst3|h[1]~705
B1L15 = B1L26 & B1L13 & (B1_h[1] $ B1L14) # !B1L26 & B1_h[1] & (!B1L14);


--B1L22 is counter60:inst3|l[1]~574
B1L22 = B1L27 & B1_l[1] # !B1L27 & B1L28 & (B1_l[1] $ B1_l[0]);


--D1L12 is counter24:inst4|l[1]~843
D1L12 = D1L17 & D1_l[1] # !D1L17 & D1L19 & (D1_l[1] $ D1_l[0]);


--B2L13 is counter60:inst|h[1]~690
B2L13 = !B2_h[0] & !B2_h[1] # !B2_h[2];


--B2L14 is counter60:inst|h[1]~691
B2L14 = B2L20 & B2_h[0] & B2L10 # !B2L20 & (B2_h[2]);


--B2L15 is counter60:inst|h[1]~692
B2L15 = B2L20 & B2L13 & (B2_h[1] $ B2L14) # !B2L20 & B2_h[1] & (!B2L14);


--B2L25 is counter60:inst|l[1]~564
B2L25 = B2L21 & B2_l[1] # !B2L21 & B2L22 & (B2_l[1] $ B2_l[0]);


--D1L6 is counter24:inst4|h[1]~334
D1L6 = D1_l[2] # D1_l[3] # !D1_l[1] # !D1_l[0];


--D1L7 is counter24:inst4|h[1]~335
D1L7 = D1_h[0] & (D1_h[1] # A1L23) # !D1_h[0] & D1_h[1] & D1L6;


--B1L1 is counter60:inst3|add~216
B1L1 = B1_l[0] & B1_l[1];


--B1L24 is counter60:inst3|l[2]~575
B1L24 = B1L27 & B1_l[2] # !B1L27 & B1L28 & (B1_l[2] $ B1L1);


--B2L1 is counter60:inst|add~216
B2L1 = B2_h[0] & B2L10;


--B2L17 is counter60:inst|h[2]~693
B2L17 = B2_h[1] & B2L20 & B2L1 & !B2_h[2] # !B2_h[1] & B2_h[2] & (!B2L1 # !B2L20);


--B2L2 is counter60:inst|add~217
B2L2 = B2_l[0] & B2_l[1];


--B2L27 is counter60:inst|l[2]~565
B2L27 = B2L21 & B2_l[2] # !B2L21 & B2L22 & (B2_l[2] $ B2L2);


--B1L2 is counter60:inst3|add~217
B1L2 = B1_h[0] & B1L10;


--B1L17 is counter60:inst3|h[2]~706
B1L17 = B1_h[1] & B1L26 & B1L2 & !B1_h[2] # !B1_h[1] & B1_h[2] & (!B1L2 # !B1L26);


--D1L14 is counter24:inst4|l[2]~844
D1L14 = D1L17 & D1_l[2] # !D1L17 & D1L19 & (D1_l[2] $ D1L22);


--D1L1 is counter24:inst4|add~146
D1L1 = D1_l[0] & D1_l[1] & D1_l[2];


--D1L20 is counter24:inst4|l[3]~845
D1L20 = D1L17 & D1_l[3] # !D1L17 & D1L19 & (D1_l[3] $ D1L1);


--B1L3 is counter60:inst3|add~218
B1L3 = B1_l[0] & B1_l[1] & B1_l[2];


--B1L29 is counter60:inst3|l[3]~576
B1L29 = B1L27 # B1L28 & (B1_l[3] $ B1L3);


--B2L3 is counter60:inst|add~218
B2L3 = B2_l[0] & B2_l[1] & B2_l[2];


--B2L29 is counter60:inst|l[3]~566
B2L29 = B2L21 # B2L22 & (B2_l[3] $ B2L3);


--F1L1 is div_clock:inst6|add~371
F1L1 = F1_count1[0] $ VCC;

--F1L2 is div_clock:inst6|add~372
F1L2 = CARRY(F1_count1[0]);


--F1L3 is div_clock:inst6|add~373
F1L3 = F1_count1[1] & !F1L2 # !F1_count1[1] & (F1L2 # GND);

--F1L4 is div_clock:inst6|add~374
F1L4 = CARRY(!F1L2 # !F1_count1[1]);


--F1L5 is div_clock:inst6|add~375
F1L5 = F1_count1[2] & (F1L4 $ GND) # !F1_count1[2] & !F1L4 & VCC;

--F1L6 is div_clock:inst6|add~376
F1L6 = CARRY(F1_count1[2] & !F1L4);


--F1L7 is div_clock:inst6|add~377
F1L7 = F1_count1[3] & !F1L6 # !F1_count1[3] & (F1L6 # GND);

--F1L8 is div_clock:inst6|add~378
F1L8 = CARRY(!F1L6 # !F1_count1[3]);


--F1L9 is div_clock:inst6|add~379
F1L9 = F1_count1[4] & (F1L8 $ GND) # !F1_count1[4] & !F1L8 & VCC;

--F1L10 is div_clock:inst6|add~380
F1L10 = CARRY(F1_count1[4] & !F1L8);


--F1L11 is div_clock:inst6|add~381
F1L11 = F1_count1[5] & !F1L10 # !F1_count1[5] & (F1L10 # GND);

--F1L12 is div_clock:inst6|add~382
F1L12 = CARRY(!F1L10 # !F1_count1[5]);


--F1L13 is div_clock:inst6|add~383
F1L13 = F1_count1[6] & (F1L12 $ GND) # !F1_count1[6] & !F1L12 & VCC;

--F1L14 is div_clock:inst6|add~384
F1L14 = CARRY(F1_count1[6] & !F1L12);


--F1L15 is div_clock:inst6|add~385
F1L15 = F1_count1[7] & !F1L14 # !F1_count1[7] & (F1L14 # GND);

--F1L16 is div_clock:inst6|add~386
F1L16 = CARRY(!F1L14 # !F1_count1[7]);


--F1L17 is div_clock:inst6|add~387
F1L17 = F1_count1[8] & (F1L16 $ GND) # !F1_count1[8] & !F1L16 & VCC;

--F1L18 is div_clock:inst6|add~388
F1L18 = CARRY(F1_count1[8] & !F1L16);


--F1L19 is div_clock:inst6|add~389
F1L19 = F1_count1[9] & !F1L18 # !F1_count1[9] & (F1L18 # GND);

--F1L20 is div_clock:inst6|add~390
F1L20 = CARRY(!F1L18 # !F1_count1[9]);


--F1L21 is div_clock:inst6|add~391
F1L21 = F1_count1[10] & (F1L20 $ GND) # !F1_count1[10] & !F1L20 & VCC;

--F1L22 is div_clock:inst6|add~392
F1L22 = CARRY(F1_count1[10] & !F1L20);


--F1L23 is div_clock:inst6|add~393
F1L23 = F1_count1[11] & !F1L22 # !F1_count1[11] & (F1L22 # GND);

--F1L24 is div_clock:inst6|add~394
F1L24 = CARRY(!F1L22 # !F1_count1[11]);


--F1L25 is div_clock:inst6|add~395
F1L25 = F1_count1[12] $ !F1L24;


--F1L59 is div_clock:inst6|count1~331
F1L59 = F1L25 & !A1L21;


--F1L60 is div_clock:inst6|count1~332
F1L60 = F1L19 & !A1L21;


--F1L61 is div_clock:inst6|count1~333
F1L61 = F1L17 & !A1L21;


--F1L62 is div_clock:inst6|count1~334
F1L62 = F1L15 & !A1L21;


--F1L63 is div_clock:inst6|count1~335
F1L63 = F1L7 & !A1L21;


--F1L64 is div_clock:inst6|count1~336
F1L64 = F1L1 & !A1L21;


--F1L72 is div_clock:inst6|count2~136
F1L72 = F1_count2[1] & (F1_count2[2] $ F1_count2[0]) # !F1_count2[1] & F1_count2[2] & (F1_count2[3] # !F1_count2[0]);


--F1L27 is div_clock:inst6|add~397
F1L27 = F1_count2[1] & F1_count2[0];


--F1L71 is div_clock:inst6|count2[3]~137
F1L71 = F1_count2[3] $ (A1L21 & F1_count2[2] & F1L27);


--F1L73 is div_clock:inst6|count2~138
F1L73 = F1_count2[1] & (!F1_count2[0]) # !F1_count2[1] & F1_count2[0] & (F1_count2[3] # !F1_count2[2]);


--B2L5 is counter60:inst|cout~342
B2L5 = B2_h[0] & B2_h[2] & !B2_h[1];


--B2L6 is counter60:inst|cout~343
B2L6 = B2_cout & (B2L20 # B2L5 # !B2L13);


--B2L7 is counter60:inst|cout~344
B2L7 = B2L6 # B2L10 & B2L20 & B2L5;


--G1L5 is sel_mode:inst9|mode[1]~6
G1L5 = G1_mode[0] $ G1_mode[1];


--B1L5 is counter60:inst3|cout~318
B1L5 = B1_h[0] & B1_h[2] & !B1_h[1];


--B1L6 is counter60:inst3|cout~319
B1L6 = B1L5 & (B1_cout # B1L26 & B1L10);


--B1L7 is counter60:inst3|cout~320
B1L7 = B1L6 # B1_cout & (B1L26 # !B1L13);


--F1_count3[5] is div_clock:inst6|count3[5]
F1_count3[5] = DFFEAS(F1L81, CLK,  ,  , F1L43,  ,  ,  ,  );


--F1_count3[4] is div_clock:inst6|count3[4]
F1_count3[4] = DFFEAS(F1L82, CLK,  ,  , F1L43,  ,  ,  ,  );


--F1_count3[3] is div_clock:inst6|count3[3]
F1_count3[3] = DFFEAS(F1L34, CLK,  ,  , F1L43,  ,  ,  ,  );


--F1_count3[2] is div_clock:inst6|count3[2]
F1_count3[2] = DFFEAS(F1L32, CLK,  ,  , F1L43,  ,  ,  ,  );


--A1L24 is rtl~212
A1L24 = F1_count3[5] & F1_count3[4] & !F1_count3[3] & !F1_count3[2];


--F1_count3[1] is div_clock:inst6|count3[1]
F1_count3[1] = DFFEAS(F1L83, CLK,  ,  , F1L43,  ,  ,  ,  );


--F1_count3[0] is div_clock:inst6|count3[0]
F1_count3[0] = DFFEAS(F1L84, CLK,  ,  , F1L43,  ,  ,  ,  );


--A1L17 is rtl~7
A1L17 = A1L24 & F1_count3[1] & !F1_count3[0];


--F1L41 is div_clock:inst6|clk_1~15
F1L41 = F1_clk_1 $ (A1L21 & A1L22 & A1L17);


--F1L28 is div_clock:inst6|add~398
F1L28 = F1_count3[0] $ VCC;

--F1L29 is div_clock:inst6|add~399
F1L29 = CARRY(F1_count3[0]);


--F1L30 is div_clock:inst6|add~400
F1L30 = F1_count3[1] & !F1L29 # !F1_count3[1] & (F1L29 # GND);

--F1L31 is div_clock:inst6|add~401
F1L31 = CARRY(!F1L29 # !F1_count3[1]);


--F1L32 is div_clock:inst6|add~402
F1L32 = F1_count3[2] & (F1L31 $ GND) # !F1_count3[2] & !F1L31 & VCC;

--F1L33 is div_clock:inst6|add~403
F1L33 = CARRY(F1_count3[2] & !F1L31);


--F1L34 is div_clock:inst6|add~404
F1L34 = F1_count3[3] & !F1L33 # !F1_count3[3] & (F1L33 # GND);

--F1L35 is div_clock:inst6|add~405
F1L35 = CARRY(!F1L33 # !F1_count3[3]);


--F1L36 is div_clock:inst6|add~406
F1L36 = F1_count3[4] & (F1L35 $ GND) # !F1_count3[4] & !F1L35 & VCC;

--F1L37 is div_clock:inst6|add~407
F1L37 = CARRY(F1_count3[4] & !F1L35);


--F1L38 is div_clock:inst6|add~408
F1L38 = F1_count3[5] $ F1L37;


--F1L81 is div_clock:inst6|count3~164
F1L81 = F1L38 & (F1_count3[0] # !F1_count3[1] # !A1L24);


--F1L82 is div_clock:inst6|count3~165
F1L82 = F1L36 & (F1_count3[0] # !F1_count3[1] # !A1L24);


--F1L83 is div_clock:inst6|count3~166
F1L83 = F1L30 & (F1_count3[0] # !F1_count3[1] # !A1L24);


--F1L84 is div_clock:inst6|count3~167
F1L84 = F1L28 & (F1_count3[0] # !F1_count3[1] # !A1L24);


--C1L3 is disp:inst2|count[0]~48
C1L3 = !C1_count[0];


--F1L44 is div_clock:inst6|clk_100~13
F1L44 = !F1_clk_100;


--F1L67 is div_clock:inst6|count2[0]~139
F1L67 = !F1_count2[0];


--G1L3 is sel_mode:inst9|mode[0]~7
G1L3 = !G1_mode[0];


--RESET is RESET
--operation mode is input

RESET = INPUT();


--CLK is CLK
--operation mode is input

CLK = INPUT();


--KEY_CHANGE is KEY_CHANGE
--operation mode is input

KEY_CHANGE = INPUT();


--KEY_MODE is KEY_MODE
--operation mode is input

KEY_MODE = INPUT();


--dp is dp
--operation mode is output

dp = OUTPUT(C1_dp);


--disp[6] is disp[6]
--operation mode is output

disp[6] = OUTPUT(E1L7);


--disp[5] is disp[5]
--operation mode is output

disp[5] = OUTPUT(!E1L6);


--disp[4] is disp[4]
--operation mode is output

disp[4] = OUTPUT(!E1L5);


--disp[3] is disp[3]
--operation mode is output

disp[3] = OUTPUT(!E1L4);


--disp[2] is disp[2]
--operation mode is output

disp[2] = OUTPUT(!E1L3);


--disp[1] is disp[1]
--operation mode is output

disp[1] = OUTPUT(!E1L2);


--disp[0] is disp[0]
--operation mode is output

disp[0] = OUTPUT(!E1L1);


--sel[5] is sel[5]
--operation mode is output

sel[5] = OUTPUT(C1_sel[5]);


--sel[4] is sel[4]
--operation mode is output

sel[4] = OUTPUT(C1_sel[4]);


--sel[3] is sel[3]
--operation mode is output

sel[3] = OUTPUT(C1_sel[3]);


--sel[2] is sel[2]
--operation mode is output

sel[2] = OUTPUT(C1_sel[2]);


--sel[1] is sel[1]
--operation mode is output

sel[1] = OUTPUT(C1_sel[1]);


--sel[0] is sel[0]
--operation mode is output

sel[0] = OUTPUT(C1_sel[0]);