clock.map.rpt

原创：基于VHDL语言编写的电子钟。采用模块化编写

; disp.vhd                         ; yes             ; User VHDL File                     ; D:/quartus/myproject/clock/disp.vhd        ;
; div_clock.vhd                    ; yes             ; User VHDL File                     ; D:/quartus/myproject/clock/div_clock.vhd   ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total combinational functions               ; 134   ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 70    ;
;     -- 3 input functions                    ; 24    ;
;     -- <=2 input functions                  ; 40    ;
;         -- Combinational cells for routing  ; 0     ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 117   ;
;     -- arithmetic mode                      ; 17    ;
; Total registers                             ; 63    ;
; I/O pins                                    ; 18    ;
; Maximum fan-out node                        ; RESET ;
; Maximum fan-out                             ; 38    ;
; Total fan-out                               ; 614   ;
; Average fan-out                             ; 2.86  ;
+---------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                               ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name      ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------+
; |clock                     ; 134 (11)          ; 63 (0)       ; 0           ; 0            ; 0       ; 0         ; 18   ; 0            ; |clock                   ;
;    |bcd_decoder:inst5|     ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |clock|bcd_decoder:inst5 ;
;    |counter24:inst4|       ; 14 (14)           ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |clock|counter24:inst4   ;
;    |counter60:inst3|       ; 19 (19)           ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |clock|counter60:inst3   ;
;    |counter60:inst|        ; 19 (19)           ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |clock|counter60:inst    ;
;    |disp:inst2|            ; 25 (25)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |clock|disp:inst2        ;
;    |div_clock:inst6|       ; 37 (37)           ; 25 (25)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |clock|div_clock:inst6   ;
;    |sel_mode:inst9|        ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |clock|sel_mode:inst9    ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 63    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 38    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 10    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
; 8:1                ; 2 bits    ; 10 LEs        ; 8 LEs                ; 2 LEs                  ; Yes        ; |clock|disp:inst2|disp[0]   ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |clock|counter60:inst|l[0]  ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |clock|counter60:inst3|l[3] ;
; 6:1                ; 3 bits    ; 12 LEs        ; 3 LEs                ; 9 LEs                  ; Yes        ; |clock|counter60:inst|h[1]  ;
; 6:1                ; 3 bits    ; 12 LEs        ; 3 LEs                ; 9 LEs                  ; Yes        ; |clock|counter60:inst3|h[2] ;
; 6:1                ; 2 bits    ; 8 LEs         ; 2 LEs                ; 6 LEs                  ; Yes        ; |clock|counter24:inst4|h[1] ;
; 7:1                ; 4 bits    ; 16 LEs        ; 4 LEs                ; 12 LEs                 ; Yes        ; |clock|counter24:inst4|l[3] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/quartus/myproject/clock/clock.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Tue Nov 11 22:54:30 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock
Info: Found 1 design units, including 1 entities, in source file clock.bdf
    Info: Found entity 1: clock
Info: Found 2 design units, including 1 entities, in source file counter60.vhd
    Info: Found design unit 1: counter60-behave
    Info: Found entity 1: counter60
Info: Found 2 design units, including 1 entities, in source file counter24.vhd
    Info: Found design unit 1: counter24-beh
    Info: Found entity 1: counter24
Info: Found 2 design units, including 1 entities, in source file bcd_decoder.vhd
    Info: Found design unit 1: bcd_decoder-one
    Info: Found entity 1: bcd_decoder
Info: Found 2 design units, including 1 entities, in source file sel_mode.vhd
    Info: Found design unit 1: sel_mode-beh
    Info: Found entity 1: sel_mode
Info: Found 2 design units, including 1 entities, in source file disp.vhd
    Info: Found design unit 1: disp-beh
    Info: Found entity 1: disp
Info: Found 2 design units, including 1 entities, in source file div_clock.vhd
    Info: Found design unit 1: div_clock-beh
    Info: Found entity 1: div_clock
Info: Elaborating entity "clock" for the top level hierarchy
Info: Elaborating entity "disp" for hierarchy "disp:inst2"
Info: Elaborating entity "div_clock" for hierarchy "div_clock:inst6"
Info: Elaborating entity "counter24" for hierarchy "counter24:inst4"
Info: Elaborating entity "counter60" for hierarchy "counter60:inst3"
Info: Elaborating entity "sel_mode" for hierarchy "sel_mode:inst9"
Info (10425): VHDL Case Statement information at sel_mode.vhd(32): OTHERS choice is never selected
Info: Elaborating entity "bcd_decoder" for hierarchy "bcd_decoder:inst5"
Info (10425): VHDL Case Statement information at bcd_decoder.vhd(32): OTHERS choice is never selected
Info: Implemented 153 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 14 output pins
    Info: Implemented 135 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Tue Nov 11 22:54:48 2008
    Info: Elapsed time: 00:00:21