clock.fit.talkback.xml

原创：基于VHDL语言编写的电子钟。采用模块化编写

		<pin__>Y13</pin__>
		<i_o_bank>7</i_o_bank>
		<x_coordinate>42</x_coordinate>
		<y_coordinate>0</y_coordinate>
		<cell_number>2</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">0</load>
	</row>
	<row>
		<name>sel[5]</name>
		<pin__>Y7</pin__>
		<i_o_bank>8</i_o_bank>
		<x_coordinate>7</x_coordinate>
		<y_coordinate>0</y_coordinate>
		<cell_number>3</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">0</load>
	</row>
</output_pins>
<i_o_bank_usage>
	<row>
		<i_o_bank>1</i_o_bank>
		<usage>2 / 46 ( 4 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
	<row>
		<i_o_bank>2</i_o_bank>
		<usage>4 / 39 ( 10 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
	<row>
		<i_o_bank>3</i_o_bank>
		<usage>2 / 39 ( 5 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
	<row>
		<i_o_bank>4</i_o_bank>
		<usage>3 / 36 ( 8 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
	<row>
		<i_o_bank>5</i_o_bank>
		<usage>2 / 44 ( 5 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
	<row>
		<i_o_bank>6</i_o_bank>
		<usage>3 / 43 ( 7 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
	<row>
		<i_o_bank>7</i_o_bank>
		<usage>4 / 36 ( 11 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
	<row>
		<i_o_bank>8</i_o_bank>
		<usage>1 / 39 ( 3 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
</i_o_bank_usage>
<advanced_data___general>
	<row>
		<name>Status Code</name>
		<value>0</value>
	</row>
	<row>
		<name>Desired User Slack</name>
		<value>0</value>
	</row>
	<row>
		<name>Fit Attempts</name>
		<value>1</value>
	</row>
</advanced_data___general>
<advanced_data___placement_preparation>
	<row>
		<name>Auto Fit Point 1 - Fit Attempt 1</name>
		<value>ff</value>
	</row>
	<row>
		<name>Mid Wire Use - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Mid Slack - Fit Attempt 1</name>
		<value>985567</value>
	</row>
	<row>
		<name>Internal Atom Count - Fit Attempt 1</name>
		<value>198</value>
	</row>
	<row>
		<name>LE/ALM Count - Fit Attempt 1</name>
		<value>135</value>
	</row>
	<row>
		<name>LAB Count - Fit Attempt 1</name>
		<value>14</value>
	</row>
	<row>
		<name>Outputs per Lab - Fit Attempt 1</name>
		<value>6.857</value>
	</row>
	<row>
		<name>Inputs per LAB - Fit Attempt 1</name>
		<value>7.929</value>
	</row>
	<row>
		<name>Global Inputs per LAB - Fit Attempt 1</name>
		<value>1.000</value>
	</row>
	<row>
		<name>LAB Constraint &apos;non-global clock + sync load&apos; - Fit Attempt 1</name>
		<value>0:13;1:1</value>
	</row>
	<row>
		<name>LAB Constraint &apos;non-global controls&apos; - Fit Attempt 1</name>
		<value>0:4;1:9;2:1</value>
	</row>
	<row>
		<name>LAB Constraint &apos;non-global + aclr&apos; - Fit Attempt 1</name>
		<value>0:4;1:9;2:1</value>
	</row>
	<row>
		<name>LAB Constraint &apos;global non-clock non-aclr&apos; - Fit Attempt 1</name>
		<value>0:14</value>
	</row>
	<row>
		<name>LAB Constraint &apos;global controls&apos; - Fit Attempt 1</name>
		<value>0:4;1:6;2:4</value>
	</row>
	<row>
		<name>LAB Constraint &apos;deterministic LABSMUXA/LABXMUXB&apos; - Fit Attempt 1</name>
		<value>0:4;1:9;2:1</value>
	</row>
	<row>
		<name>LAB Constraint &apos;deterministic LABSMUXC/LABXMUXD&apos; - Fit Attempt 1</name>
		<value>0:9;1:5</value>
	</row>
	<row>
		<name>LAB Constraint &apos;clock / ce pair constraint&apos; - Fit Attempt 1</name>
		<value>0:4;1:2;2:8</value>
	</row>
	<row>
		<name>LAB Constraint &apos;aclr constraint&apos; - Fit Attempt 1</name>
		<value>0:4;1:10</value>
	</row>
	<row>
		<name>LAB Constraint &apos;true sload_sclear pair&apos; - Fit Attempt 1</name>
		<value>0:14</value>
	</row>
	<row>
		<name>LAB Constraint &apos;constant sload_sclear pair&apos; - Fit Attempt 1</name>
		<value>0:14</value>
	</row>
	<row>
		<name>LAB Constraint &apos;has placement constraint&apos; - Fit Attempt 1</name>
		<value>0:14</value>
	</row>
	<row>
		<name>LEs in Chains - Fit Attempt 1</name>
		<value>19</value>
	</row>
	<row>
		<name>LEs in Long Chains - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>LABs with Chains - Fit Attempt 1</name>
		<value>2</value>
	</row>
	<row>
		<name>LABs with Multiple Chains - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Time - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Time in tsm_tan.dll - Fit Attempt 1</name>
		<value>0.060</value>
	</row>
</advanced_data___placement_preparation>
<advanced_data___placement>
	<row>
		<name>Auto Fit Point 2 - Fit Attempt 1</name>
		<value>ff</value>
	</row>
	<row>
		<name>Early Wire Use - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Early Slack - Fit Attempt 1</name>
		<value>981898</value>
	</row>
	<row>
		<name>Auto Fit Point 3 - Fit Attempt 1</name>
		<value>ff</value>
	</row>
	<row>
		<name>Mid Wire Use - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Mid Slack - Fit Attempt 1</name>
		<value>983537</value>
	</row>
	<row>
		<name>Auto Fit Point 4 - Fit Attempt 1</name>
		<value>ff</value>
	</row>
	<row>
		<name>Late Wire Use - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Late Slack - Fit Attempt 1</name>
		<value>983537</value>
	</row>
	<row>
		<name>Auto Fit Point 5 - Fit Attempt 1</name>
		<value>ff</value>
	</row>
	<row>
		<name>Time - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Time in tsm_dat.dll - Fit Attempt 1</name>
		<value>0.010</value>
	</row>
	<row>
		<name>Time in tsm_tan.dll - Fit Attempt 1</name>
		<value>0.150</value>
	</row>
</advanced_data___placement>
<advanced_data___routing>
	<row>
		<name>Early Slack - Fit Attempt 1</name>
		<value>984164</value>
	</row>
	<row>
		<name>Early Wire Use - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Peak Regional Wire - Fit Attempt 1</name>
		<value>1</value>
	</row>
	<row>
		<name>Mid Slack - Fit Attempt 1</name>
		<value>982448</value>
	</row>
	<row>
		<name>Late Slack - Fit Attempt 1</name>
		<value>982448</value>
	</row>
	<row>
		<name>Late Slack - Fit Attempt 1</name>
		<value>982448</value>
	</row>
	<row>
		<name>Late Wire Use - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Time - Fit Attempt 1</name>
		<value>4</value>
	</row>
	<row>
		<name>Time in tsm_tan.dll - Fit Attempt 1</name>
		<value>0.420</value>
	</row>
</advanced_data___routing>
<compilation_summary>
	<flow_status>Successful - Tue Nov 11 22:55:47 2008</flow_status>
	<quartus_ii_version>5.1 Build 176 10/26/2005 SJ Full Version</quartus_ii_version>
	<revision_name>clock</revision_name>
	<top_level_entity_name>clock</top_level_entity_name>
	<family>Cyclone II</family>
	<device>EP2C35F484C8</device>
	<timing_models>Preliminary</timing_models>
	<met_timing_requirements>N/A</met_timing_requirements>
	<total_logic_elements>134 / 33,216 ( &lt; 1 % )</total_logic_elements>
	<total_registers>63</total_registers>
	<total_pins>18 / 322 ( 6 % )</total_pins>
	<total_virtual_pins>0</total_virtual_pins>
	<total_memory_bits>0 / 483,840 ( 0 % )</total_memory_bits>
	<embedded_multiplier_9_bit_elements>0 / 70 ( 0 % )</embedded_multiplier_9_bit_elements>
	<total_plls>0 / 4 ( 0 % )</total_plls>
</compilation_summary>
<compile_id>F27B02F2</compile_id>
<files>
	<top>D:/quartus/myproject/clock/clock.bdf</top>
	<extensions>
		<ext ext_name="bdf">1</ext>
		<ext ext_name="vhd">6</ext>
		<ext ext_name="vwf">1</ext>
	</extensions>
	<sub_files>
		<sub_file>D:/quartus/myproject/clock/clock.bdf</sub_file>
		<sub_file>D:/quartus/myproject/clock/counter60.vhd</sub_file>
		<sub_file>D:/quartus/myproject/clock/counter24.vhd</sub_file>
		<sub_file>D:/quartus/myproject/clock/bcd_decoder.vhd</sub_file>
		<sub_file>D:/quartus/myproject/clock/sel_mode.vhd</sub_file>
		<sub_file>D:/quartus/myproject/clock/clock.vwf</sub_file>
		<sub_file>D:/quartus/myproject/clock/disp.vhd</sub_file>
		<sub_file>D:/quartus/myproject/clock/div_clock.vhd</sub_file>
	</sub_files>
</files>
<architecture>
	<family>Cyclone II</family>
	<auto_device>OFF</auto_device>
	<device>EP2C35F484C8</device>
</architecture>
<pkg_io>
	<pin_std count="21">LVTTL</pin_std>
</pkg_io>
</talkback>