prev_cmp_mul16.map.qmsg

基于CPLD/FPGA的十六位乘法器的VHDL实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 14 20:31:07 2008 " "Info: Processing started: Fri Nov 14 20:31:07 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off mul16 -c mul16 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off mul16 -c mul16" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mul16.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file mul16.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mul16-behave " "Info: Found design unit 1: mul16-behave" {  } { { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mul16 " "Info: Found entity 1: mul16" {  } { { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "mul16 " "Info: Elaborating entity \"mul16\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Error" "EVRFX_VHDL_EXPR_ELEMENT_NUMBER_MISMATCH" "32 16 mul16.vhd(30) " "Error (10344): VHDL expression error at mul16.vhd(30): expression has 32 elements, but must have 16 elements" {  } { { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 30 0 0 } }  } 0 10344 "VHDL expression error at %3!s!: expression has %1!d! elements, but must have %2!d! elements" 0 0 "" 0 0}
{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Error: Can't elaborate top-level user hierarchy" {  } {  } 0 0 "Can't elaborate top-level user hierarchy" 0 0 "" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "171 " "Error: Peak virtual memory: 171 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Error" "EQEXE_END_BANNER_TIME" "Fri Nov 14 20:31:11 2008 " "Error: Processing ended: Fri Nov 14 20:31:11 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:04 " "Error: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Error: Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}