ubs_fifo.txt

同步写USB_SLAVE_FIFO的VHDL源代码

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity usb_fifo is
		
	port(USBIFCLK, USBFULL : in std_logic;
	
			SRAMAD, SRAMBD : in std_logic_vector(15 downto 0);
			
			SRAMA : in std_logic_vector(15 downto 0);
			
			SRAMOE, SLWR : out std_logic;
			
			SRAMACE, SRAMBCE : out std_logic;
			
			FIFOADR : out std_logic_vector(1 downto 0);
			
			USBFD : out std_logic_vector(15 downto 0)
		);
		
end;

architecture behavior of usb_fifo is
		
	type states is (st0, st1, st2, st3, st4, St5, st6, st7);
	
	signal current_state, next_state : states := st0;
	
	begin
---------------------------------------------------------------------------------------------------		
	process(current_state, USBFULL, SRAMA, SRAMAD, SRAMBD)
		
		begin
		
		case current_state is
		
			when st0 => SRAMOE <= '1'; SLWR <= '1'; USBFD <= "ZZZZZZZZZZZZZZZZ";
			
						SRAMACE <= '0'; SRAMBCE <= '1'; FIFOADR <= "11"; next_state <= st1;
			
			when st1 => SRAMOE <= '1'; SLWR <= '1'; USBFD <= "ZZZZZZZZZZZZZZZZ";
			
						SRAMACE <= '0'; SRAMBCE <= '1';
			
						if(USBFULL = '0') then next_state <= st2;
		
						else next_state <= st1;
		
						end if;
			
			when st2 => SRAMOE <= '0'; SLWR <= '0'; SRAMACE <= '0'; SRAMBCE <= '1';
			
						USBFD <= SRAMAD; next_state <= st3;
			
			when st3 => if(SRAMA = "0000000000000111") then
		
							next_state <= st4;
							
						else next_state <= st0;
		
						end if;
							
			when st4 => SRAMOE <= '1'; SLWR <= '1'; USBFD <= "ZZZZZZZZZZZZZZZZ";
			
						SRAMACE <= '1'; SRAMBCE <= '0'; FIFOADR <= "11"; next_state <= st5;
			
			when st5 => SRAMOE <= '1'; SLWR <= '1'; USBFD <= "ZZZZZZZZZZZZZZZZ";
			
						SRAMACE <= '1'; SRAMBCE <= '0';
			
						if(USBFULL = '0') then next_state <= st6;
		
						else next_state <= st5;
		
						end if;
			
			when st6 => SRAMOE <= '0'; SLWR <= '0'; SRAMACE <= '1'; SRAMBCE <= '0'; 
			
						USBFD <= SRAMBD; next_state <= st7;
						
			when st7 => if(SRAMA = "0000000000000111") then
		
							next_state <= st0;
							
						else next_state <= st4;
		
						end if;
						
			when others => SRAMOE <= '1'; SLWR <= '1'; USBFD <= "ZZZZZZZZZZZZZZZZ";
			
						 next_state <= st0;
		
		end case;
		
	end process;
	
-------------------------------------------------------------------------------------------------
	
	process(USBIFCLK)
		
		begin
		
		if(USBIFCLK'event and USBIFCLK = '1') then
		
			current_state <= next_state;
			
		end if;
		
	end process;
--------------------------------------------------------------------------------------------------
end;	
		117.69.73.187	
		





library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity write_read_control is

	port(SRAMWE_TEMP, SRAMOE_TEMP : in std_logic;
		
			ADCLK0_TEMP : in std_logic;

			SRAMA : in std_logic_vector(15 downto 0);
		
			SRAMWE, SRAMOE : out std_logic;
		
			SRAMACE, SRAMBCE : out std_logic;
			
			ADCLK0 : out std_logic
		
		);
end;

architecture behavior of write_read_control is

	type states is(st0, st1);
	
	signal current_state, next_state : states := st0;

	begin
--------------------------------------------------------------------------------------------
	process(current_state, SRAMWE_TEMP, SRAMOE_TEMP, ADCLK0_TEMP, SRAMA)

		begin

		case current_state is

			when st0 => ADCLK0 <= ADCLK0_TEMP; SRAMWE <= SRAMWE_TEMP;
			
						 SRAMOE <= '1'; SRAMACE <= '0'; SRAMBCE <= '1';
						
						if(SRAMA = "0000000000001111") then
						
							next_state <= st1;
						
						else next_state <= st0;	
						
						end if;
						
			when st1 => ADCLK0 <= '0'; SRAMWE <= '1'; 
			
						SRAMOE <= SRAMOE_TEMP; SRAMACE <= '0'; SRAMBCE <= '1';
						
						if(SRAMA = "0000000000001111") then
							
							next_state <= st0;
							
						else next_state <= st1;
	
						end if;
	
			when others =>
			
		end case;
		
	end process;
-------------------------------------------------------------------------------------------------
	process(ADCLK0_TEMP)

		begin
		
		if(ADCLK0_TEMP' event and ADCLK0_TEMP = '0') then

			current_state <= next_state;
			
		end if;
		
	end process;			
-----------------------------------------------------------------------
end;