digital_clk.tan.qmsg

来自「该工程的主要功能是由VHDL语言实现多功能数字电子时钟」· QMSG 代码 · 共 17 行 · 第 1/5 页

{ "Info" "ITDB_FULL_TPD_RESULT" "set12 seg7\[1\] 25.100 ns Shortest " "Info: Shortest tpd from source pin set12 to destination pin seg7\[1\] is 25.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns set12 1 PIN Pin_6 3 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = Pin_6; Fanout = 3; PIN Node = 'set12'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "" { set12 } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(1.900 ns) 8.500 ns data\[1\]~1097 2 COMB LC5_B10 1 " "Info: 2: + IC(3.500 ns) + CELL(1.900 ns) = 8.500 ns; Loc. = LC5_B10; Fanout = 1; COMB Node = 'data\[1\]~1097'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "5.400 ns" { set12 data[1]~1097 } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.400 ns) 10.500 ns data\[1\]~1100 3 COMB LC3_B10 1 " "Info: 3: