digital_clk.tan.qmsg

来自「该工程的主要功能是由VHDL语言实现多功能数字电子时钟」· QMSG 代码 · 共 17 行 · 第 1/5 页

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITAN_SCC_LOOP" "2 " "Info: Found combinational loop of 2 nodes" { { "Info" "ITAN_SCC_NODE" "blink\[2\]~32 " "Info: Node blink\[2\]~32" {  } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 23 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "blink\[2\]~331 " "Info: Node blink\[2\]~331" {  } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 23 -1 0 } }  } 0}  } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 23 -1 0 } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 23 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "2 " "Info: Found combinational loop of 2 nodes" { { "Info" "ITAN_SCC_NODE" "blink\[0\]~31 " "Info: Node blink\[0\]~31" {  } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 23 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "blink\[0\]~329 " "Info: Node blink\[0\]~329" {  } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 23 -1 0 } }  } 0}  } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 23 -1 0 } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 23 -1 0 } }  } 0}
{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 5 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0} { "Info" "ITDB_NODE_MAP_TO_CLK" "mode " "Info: Assuming node mode is an undefined clock" {  } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 10 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "mode" } } } }  } 0}  } {  } 0}