digital_clk.tan.qmsg

来自「该工程的主要功能是由VHDL语言实现多功能数字电子时钟」· QMSG 代码 · 共 17 行 · 第 1/5 页

{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg7\[6\] hour_display\[3\] 57.100 ns register " "Info: tco from clock clk to destination pin seg7\[6\] through register hour_display\[3\] is 57.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 13.500 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 13.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK Pin_1 16 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_1; Fanout = 16; CLK Node = 'clk'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.900 ns) 4.800 ns clk1khz 2 REG LC5_B2 25 " "Info: 2: + IC(2.000 ns) + CELL(0.900 ns) = 4.800 ns; Loc. = LC5_B2; Fanout = 25; REG Node = 'clk1khz'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "2.900 ns" { clk clk1khz } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(0.900 ns) 8.800 ns clk1hz 3 REG LC1_B13 52 " "Info: 3: + IC(3.100 ns) + CELL(0.900 ns) = 8.800 ns; Loc. = LC1_B13; Fanout = 52; REG Node = 'clk1hz'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "4.000 ns" { clk1khz clk1hz } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 47 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.700 ns) + CELL(0.000 ns) 13.500 ns hour_display\[3\] 4 REG LC8_A20 8 " "Info: 4: + IC(4.700 ns) + CELL(0.000 ns) = 13.500 ns; Loc. = LC8_A20; Fanout = 8; REG Node = 'hour_display\[3\]'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "4.700 ns" { clk1hz hour_display[3] } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 75 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.700 ns 27.41 % " "Info: Total cell delay = 3.700 ns ( 27.41 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.800 ns 72.59 % " "Info: Total interconnect delay = 9.800 ns ( 72.59 % )" {  } {  } 0}  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "13.500 ns" { clk clk1khz clk1hz hour_display[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 75 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "42.700 ns + Longest register pin " "Info: + Longest register to pin delay is 42.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns hour_display\[3\] 1 REG LC8_A20 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_A20; Fanout = 8; REG Node = 'hour_display\[3\]'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "" { hour_display[3] } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 75 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.600 ns) + CELL(1.900 ns) 5.500 ns lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~13 2 COMB LC6_B3 5 " "Info: 2: + IC(3.600 ns) + CELL(1.900 ns) = 5.500 ns; Loc. = LC6_B3; Fanout = 5; COMB Node = 'lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~13'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "5.500 ns" { hour_display[3] lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00009|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~13 } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 8.000 ns lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|StageOut\[3\]\[3\]~101 3 COMB LC8_B3 1 " "Info: 3: + IC(0.600 ns) + CELL(1.900 ns) = 8.000 ns; Loc. = LC8_B3; Fanout = 1; COMB Node = 'lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|StageOut\[3\]\[3\]~101'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "2.500 ns" { lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00009|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~13 lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|StageOut[3][3]~101 } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_u_div.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_u_div.tdf" 106 10 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 10.500 ns lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[4\]~39 4 COMB LC1_B3 2 " "Info: 4: + IC(0.600 ns) + CELL(1.900 ns) = 10.500 ns; Loc. = LC1_B3; Fanout = 2; COMB Node = 'lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[4\]~39'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "2.500 ns" { lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|StageOut[3][3]~101 lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00011|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~39 } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 13.000 ns i730~240 5 COMB LC5_B3 1 " "Info: 5: + IC(0.600 ns) + CELL(1.900 ns) = 13.000 ns; Loc. = LC5_B3; Fanout = 1; COMB Node = 'i730~240'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "2.500 ns" { lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00011|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~39 i730~240 } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 254 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(1.400 ns) 16.800 ns i730~241 6 COMB LC7_B8 4 " "Info: 6: + IC(2.400 ns) + CELL(1.400 ns) = 16.800 ns; Loc. = LC7_B8; Fanout = 4; COMB Node = 'i730~241'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "3.800 ns" { i730~240 i730~241 } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 254 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(1.900 ns) 21.100 ns qhl\[1\]~16 7 COMB LC2_B11 1 " "Info: 7: + IC(2.400 ns) + CELL(1.900 ns) = 21.100 ns; Loc. = LC2_B11; Fanout = 1; COMB Node = 'qhl\[1\]~16'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "4.300 ns" { i730~241 qhl[1]~16 } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.900 ns) 24.800 ns data\[1\]~1100 8 COMB LC3_B10 1 " "Info: 8: + IC(1.800 ns) + CELL(1.900 ns) = 24.800 ns; Loc. = LC3_B10; Fanout = 1; COMB Node = 'data\[1\]~1100'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "3.700 ns" { qhl[1]~16 data[1]~1100 } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(1.900 ns) 29.800 ns data\[1\]~1101 9 COMB LC2_A6 9 " "Info: 9: + IC(3.100 ns) + CELL(1.900 ns) = 29.800 ns; Loc. = LC2_A6; Fanout = 9; COMB Node = 'data\[1\]~1101'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "5.000 ns" { data[1]~1100 data[1]~1101 } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(1.900 ns) 34.900 ns i~8208 10 COMB LC4_B4 1 " "Info: 10: + IC(3.200 ns) + CELL(1.900 ns) = 34.900 ns; Loc. = LC4_B4; Fanout = 1; COMB Node = 'i~8208'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "5.100 ns" { data[1]~1101 i~8208 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.400 ns) 36.900 ns i~683 11 COMB LC3_B4 2 " "Info: 11: + IC(0.600 ns) + CELL(1.400 ns) = 36.900 ns; Loc. = LC3_B4; Fanout = 2; COMB Node = 'i~683'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "2.000 ns" { i~8208 i~683 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(3.900 ns) 42.700 ns seg7\[6\] 12 PIN Pin_17 0 " "Info: 12: + IC(1.900 ns) + CELL(3.900 ns) = 42.700 ns; Loc. = Pin_17; Fanout = 0; PIN Node = 'seg7\[6\]'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "5.800 ns" { i~683 seg7[6] } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "21.900 ns 51.29 % " "Info: Total cell delay = 21.900 ns ( 51.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "20.800 ns 48.71 % " "Info: Total interconnect delay = 20.800 ns ( 48.71 % )" {  } {  } 0}  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "42.700 ns" { hour_display[3] lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00009|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~13 lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|StageOut[3][3]~101 lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00011|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~39 i730~240 i730~241 qhl[1]~16 data[1]~1100 data[1]~1101 i~8208 i~683 seg7[6] } "NODE_NAME" } } }  } 0}  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "13.500 ns" { clk clk1khz clk1hz hour_display[3] } "NODE_NAME" } } } { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "42.700 ns" { hour_display[3] lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00009|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~13 lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|StageOut[3][3]~101 lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00011|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~39 i730~240 i730~241 qhl[1]~16 data[1]~1100 data[1]~1101 i~8208 i~683 seg7[6] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "set12 seg7\[6\] 36.300 ns Longest " "Info: Longest tpd from source pin set12 to destination pin seg7\[6\] is 36.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns set12 1 PIN Pin_6 3 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = Pin_6; Fanout = 3; PIN Node = 'set12'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "" { set12 } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(1.400 ns) 7.900 ns i731~290 2 COMB LC5_B8 2 " "Info: 2: + IC(3.400 ns) + CELL(1.400 ns) = 7.900 ns; Loc. = LC5_B8; Fanout = 2; COMB Node = 'i731~290'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "4.800 ns" { set12 i731~290 } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 254 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 10.400 ns i730~241 3 COMB LC7_B8 4 " "Info: 3: + IC(0.600 ns) + CELL(1.900 ns) = 10.400 ns; Loc. = LC7_B8; Fanout = 4; COMB Node = 'i730~241'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "2.500 ns" { i731~290 i730~241 } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 254 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(1.900 ns) 14.700 ns qhl\[1\]~16 4 COMB LC2_B11 1 " "Info: 4: + IC(2.400 ns) + CELL(1.900 ns) = 14.700 ns; Loc. = LC2_B11; Fanout = 1; COMB Node = 'qhl\[1\]~16'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "4.300 ns" { i730~241 qhl[1]~16 } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.900 ns) 18.400 ns data\[1\]~1100 5 COMB LC3_B10 1 " "Info: 5: + IC(1.800 ns) + CELL(1.900 ns) = 18.400 ns; Loc. = LC3_B10; Fanout = 1; COMB Node = 'data\[1\]~1100'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "3.700 ns" { qhl[1]~16 data[1]~1100 } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(1.900 ns) 23.400 ns data\[1\]~1101 6 COMB LC2_A6 9 " "Info: 6: + IC(3.100 ns) + CELL(1.900 ns) = 23.400 ns; Loc. = LC2_A6; Fanout = 9; COMB Node = 'data\[1\]~1101'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "5.000 ns" { data[1]~1100 data[1]~1101 } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(1.900 ns) 28.500 ns i~8208 7 COMB LC4_B4 1 " "Info: 7: + IC(3.200 ns) + CELL(1.900 ns) = 28.500 ns; Loc. = LC4_B4; Fanout = 1; COMB Node = 'i~8208'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "5.100 ns" { data[1]~1101 i~8208 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.400 ns) 30.500 ns i~683 8 COMB LC3_B4 2 " "Info: 8: + IC(0.600 ns) + CELL(1.400 ns) = 30.500 ns; Loc. = LC3_B4; Fanout = 2; COMB Node = 'i~683'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "2.000 ns" { i~8208 i~683 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(3.900 ns) 36.300 ns seg7\[6\] 9 PIN Pin_17 0 " "Info: 9: + IC(1.900 ns) + CELL(3.900 ns) = 36.300 ns; Loc. = Pin_17; Fanout = 0; PIN Node = 'seg7\[6\]'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "5.800 ns" { i~683 seg7[6] } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "19.300 ns 53.17 % " "Info: Total cell delay = 19.300 ns ( 53.17 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "17.000 ns 46.83 % " "Info: Total interconnect delay = 17.000 ns ( 46.83 % )" {  } {  } 0}  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "36.300 ns" { set12 i731~290 i730~241 qhl[1]~16 data[1]~1100 data[1]~1101 i~8208 i~683 seg7[6] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "inc_reg inc clk 7.300 ns register " "Info: th for register inc_reg (data pin = inc, clock pin = clk) is 7.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 13.500 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 13.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK Pin_1 16 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_1; Fanout = 16; CLK Node = 'clk'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.900 ns) 4.800 ns clk1khz 2 REG LC5_B2 25 " "Info: 2: + IC(2.000 ns) + CELL(0.900 ns) = 4.800 ns; Loc. = LC5_B2; Fanout = 25; REG Node = 'clk1khz'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "2.900 ns" { clk clk1khz } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(0.900 ns) 8.800 ns clk1hz 3 REG LC1_B13 52 " "Info: 3: + IC(3.100 ns) + CELL(0.900 ns) = 8.800 ns; Loc. = LC1_B13; Fanout = 52; REG Node = 'clk1hz'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "4.000 ns" { clk1khz clk1hz } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 47 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.700 ns) + CELL(0.000 ns) 13.500 ns inc_reg 4 REG LC6_A24 4 " "Info: 4: + IC(4.700 ns) + CELL(0.000 ns) = 13.500 ns; Loc. = LC6_A24; Fanout = 4; REG Node = 'inc_reg'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "4.700 ns" { clk1hz inc_reg } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 75 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.700 ns 27.41 % " "Info: Total cell delay = 3.700 ns ( 27.41 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.800 ns 72.59 % " "Info: Total interconnect delay = 9.800 ns ( 72.59 % )" {  } {  } 0}  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "13.500 ns" { clk clk1khz clk1hz inc_reg } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.400 ns + " "Info: + Micro hold delay of destination is 1.400 ns" {  } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 75 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.600 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns inc 1 PIN Pin_38 4 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = Pin_38; Fanout = 4; PIN Node = 'inc'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "" { inc } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.600 ns) + CELL(0.900 ns) 7.600 ns inc_reg 2 REG LC6_A24 4 " "Info: 2: + IC(3.600 ns) + CELL(0.900 ns) = 7.600 ns; Loc. = LC6_A24; Fanout = 4; REG Node = 'inc_reg'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "4.500 ns" { inc inc_reg } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 75 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 52.63 % " "Info: Total cell delay = 4.000 ns ( 52.63 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.600 ns 47.37 % " "Info: Total interconnect delay = 3.600 ns ( 47.37 % )" {  } {  } 0}  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "7.600 ns" { inc inc_reg } "NODE_NAME" } } }  } 0}  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "13.500 ns" { clk clk1khz clk1hz inc_reg } "NODE_NAME" } } } { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "7.600 ns" { inc inc_reg } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk scan\[1\] cnt\[0\] 13.000 ns register " "Info: Minimum tco from clock clk to destination pin scan\[1\] through register cnt\[0\] is 13.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.400 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 5.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK Pin_1 16 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_1; Fanout = 16; CLK Node = 'clk'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.900 ns) 4.800 ns clk1khz 2 REG LC5_B2 25 " "Info: 2: + IC(2.000 ns) + CELL(0.900 ns) = 4.800 ns; Loc. = LC5_B2; Fanout = 25; REG Node = 'clk1khz'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "2.900 ns" { clk clk1khz } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.000 ns) 5.400 ns cnt\[0\] 3 REG LC6_B2 19 " "Info: 3: + IC(0.600 ns) + CELL(0.000 ns) = 5.400 ns; Loc. = LC6_B2; Fanout = 19; REG Node = 'cnt\[0\]'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "0.600 ns" { clk1khz cnt[0] } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 280 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 51.85 % " "Info: Total cell delay = 2.800 ns ( 51.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns 48.15 % " "Info: Total interconnect delay = 2.600 ns ( 48.15 % )" {  } {  } 0}  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "5.400 ns" { clk clk1khz cnt[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 280 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.700 ns + Shortest register pin " "Info: + Shortest register to pin delay is 6.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[0\] 1 REG LC6_B2 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_B2; Fanout = 19; REG Node = 'cnt\[0\]'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "" { cnt[0] } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 280 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.400 ns) 2.000 ns i~197 2 COMB LC4_B2 1 " "Info: 2: + IC(0.600 ns) + CELL(1.400 ns) = 2.000 ns; Loc. = LC4_B2; Fanout = 1; COMB Node = 'i~197'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "2.000 ns" { cnt[0] i~197 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(3.900 ns) 6.700 ns scan\[1\] 3 PIN Pin_10 0 " "Info: 3: + IC(0.800 ns) + CELL(3.900 ns) = 6.700 ns; Loc. = Pin_10; Fanout = 0; PIN Node = 'scan\[1\]'" {  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "4.700 ns" { i~197 scan[1] } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.300 ns 79.10 % " "Info: Total cell delay = 5.300 ns ( 79.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 20.90 % " "Info: Total interconnect delay = 1.400 ns ( 20.90 % )" {  } {  } 0}  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "6.700 ns" { cnt[0] i~197 scan[1] } "NODE_NAME" } } }  } 0}  } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "5.400 ns" { clk clk1khz cnt[0] } "NODE_NAME" } } } { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "6.700 ns" { cnt[0] i~197 scan[1] } "NODE_NAME" } } }  } 0}