alu_cpu.hif

verilog实践 alu_cpu 算数运算器的verilog实现

Version 6.1 Build 201 11/27/2006 SJ Full Version
35
1916
OFF
OFF
OFF
OFF
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
alu_cpu
# storage
db|alu_cpu.(0).cnf
db|alu_cpu.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
alu_cpu.v
8d8b6e3268ef0831cc569ae3fab1e99
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
ADD
000
PARAMETER_UNSIGNED_BIN
DEF
ANDD
001
PARAMETER_UNSIGNED_BIN
DEF
XORR
010
PARAMETER_UNSIGNED_BIN
DEF
LDA
011
PARAMETER_UNSIGNED_BIN
DEF
STO
100
PARAMETER_UNSIGNED_BIN
DEF
JMP
101
PARAMETER_UNSIGNED_BIN
DEF
}
# hierarchies {
|
}
# end
# complete