alu_cpu.hier_info

verilog实践 alu_cpu 算数运算器的verilog实现

|alu_cpu
alu_out[0] <= alu_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
alu_out[1] <= alu_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
alu_out[2] <= alu_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
alu_out[3] <= alu_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
alu_out[4] <= alu_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
alu_out[5] <= alu_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
alu_out[6] <= alu_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
alu_out[7] <= alu_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
zero <= WideNor0.DB_MAX_OUTPUT_PORT_TYPE
data[0] => Add0.IN8
data[0] => alu_out~0.IN0
data[0] => alu_out~8.IN0
data[0] => Mux7.IN5
data[1] => Add0.IN7
data[1] => alu_out~1.IN0
data[1] => alu_out~9.IN0
data[1] => Mux6.IN5
data[2] => Add0.IN6
data[2] => alu_out~2.IN0
data[2] => alu_out~10.IN0
data[2] => Mux5.IN5
data[3] => Add0.IN5
data[3] => alu_out~3.IN0
data[3] => alu_out~11.IN0
data[3] => Mux4.IN5
data[4] => Add0.IN4
data[4] => alu_out~4.IN0
data[4] => alu_out~12.IN0
data[4] => Mux3.IN5
data[5] => Add0.IN3
data[5] => alu_out~5.IN0
data[5] => alu_out~13.IN0
data[5] => Mux2.IN5
data[6] => Add0.IN2
data[6] => alu_out~6.IN0
data[6] => alu_out~14.IN0
data[6] => Mux1.IN5
data[7] => Add0.IN1
data[7] => alu_out~7.IN0
data[7] => alu_out~15.IN0
data[7] => Mux0.IN5
accum[0] => WideNor0.IN7
accum[0] => Add0.IN16
accum[0] => alu_out~0.IN1
accum[0] => alu_out~8.IN1
accum[0] => Mux7.IN6
accum[0] => Mux7.IN7
accum[1] => WideNor0.IN6
accum[1] => Add0.IN15
accum[1] => alu_out~1.IN1
accum[1] => alu_out~9.IN1
accum[1] => Mux6.IN6
accum[1] => Mux6.IN7
accum[2] => WideNor0.IN5
accum[2] => Add0.IN14
accum[2] => alu_out~2.IN1
accum[2] => alu_out~10.IN1
accum[2] => Mux5.IN6
accum[2] => Mux5.IN7
accum[3] => WideNor0.IN4
accum[3] => Add0.IN13
accum[3] => alu_out~3.IN1
accum[3] => alu_out~11.IN1
accum[3] => Mux4.IN6
accum[3] => Mux4.IN7
accum[4] => WideNor0.IN3
accum[4] => Add0.IN12
accum[4] => alu_out~4.IN1
accum[4] => alu_out~12.IN1
accum[4] => Mux3.IN6
accum[4] => Mux3.IN7
accum[5] => WideNor0.IN2
accum[5] => Add0.IN11
accum[5] => alu_out~5.IN1
accum[5] => alu_out~13.IN1
accum[5] => Mux2.IN6
accum[5] => Mux2.IN7
accum[6] => WideNor0.IN1
accum[6] => Add0.IN10
accum[6] => alu_out~6.IN1
accum[6] => alu_out~14.IN1
accum[6] => Mux1.IN6
accum[6] => Mux1.IN7
accum[7] => WideNor0.IN0
accum[7] => Add0.IN9
accum[7] => alu_out~7.IN1
accum[7] => alu_out~15.IN1
accum[7] => Mux0.IN6
accum[7] => Mux0.IN7
alu_clk => alu_out[6]~reg0.CLK
alu_clk => alu_out[5]~reg0.CLK
alu_clk => alu_out[4]~reg0.CLK
alu_clk => alu_out[3]~reg0.CLK
alu_clk => alu_out[2]~reg0.CLK
alu_clk => alu_out[1]~reg0.CLK
alu_clk => alu_out[0]~reg0.CLK
alu_clk => alu_out[7]~reg0.CLK
opcode[0] => Mux0.IN10
opcode[0] => Mux1.IN10
opcode[0] => Mux2.IN10
opcode[0] => Mux3.IN10
opcode[0] => Mux4.IN10
opcode[0] => Mux5.IN10
opcode[0] => Mux6.IN10
opcode[0] => Mux7.IN10
opcode[1] => Mux0.IN9
opcode[1] => Mux1.IN9
opcode[1] => Mux2.IN9
opcode[1] => Mux3.IN9
opcode[1] => Mux4.IN9
opcode[1] => Mux5.IN9
opcode[1] => Mux6.IN9
opcode[1] => Mux7.IN9
opcode[2] => Mux0.IN8
opcode[2] => Mux1.IN8
opcode[2] => Mux2.IN8
opcode[2] => Mux3.IN8
opcode[2] => Mux4.IN8
opcode[2] => Mux5.IN8
opcode[2] => Mux6.IN8
opcode[2] => Mux7.IN8