alu_cpu.v

verilog实践 alu_cpu 算数运算器的verilog实现

module alu_cpu(alu_out,zero,data,accum,alu_clk,opcode);
output[7:0]alu_out;
output zero;
input[7:0]data,accum;
input[2:0]opcode;
input alu_clk;
reg[7:0] alu_out;
parameter  ADD=3'b000,
           ANDD=3'b001,
           XORR=3'b010,
           LDA=3'b011,
           STO=3'b100,
           JMP=3'b101;
assign  zero=!accum;
always@(posedge alu_clk)
  begin 
     casex(opcode)
       ADD:alu_out<=data+accum;
       ANDD:alu_out<=data&accum;
       XORR:alu_out<=data^accum;//异或
       LDA:alu_out<=data;
       STO:alu_out<=accum;
       JMP:alu_out<=accum;
       default:alu_out<=8'bxxxx_xxxx;
    endcase
  end
endmodule