full_adder.map.rpt

实现一位加法器的设计

; Auto Resource Sharing                                                          ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                                  ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                              ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                             ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                             ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                               ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Block Design Naming                                                            ; Auto               ; Auto               ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                 ;
+----------------------------------+-----------------+------------------------------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+------------------------------+
; half_adder.vhd                   ; yes             ; User VHDL File                     ; d:/jinguiyu/half_adder.vhd   ;
; full_adder.bdf                   ; yes             ; User Block Diagram/Schematic File  ; d:/jinguiyu/full_adder.bdf   ;
+----------------------------------+-----------------+------------------------------------+------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 2     ;
;                                             ;       ;
; Total combinational functions               ; 2     ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 0     ;
;     -- 3 input functions                    ; 2     ;
;     -- <=2 input functions                  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 2     ;
;     -- arithmetic mode                      ; 0     ;
;                                             ;       ;
; Total registers                             ; 0     ;
;     -- Dedicated logic registers            ; 0     ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 8     ;
; Maximum fan-out node                        ; ain   ;
; Maximum fan-out                             ; 3     ;
; Total fan-out                               ; 11    ;
; Average fan-out                             ; 1.10  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                  ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name          ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------+--------------+
; |full_adder                ; 2 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 8    ; 0            ; |full_adder                  ; work         ;
;    |half_adder:inst1|      ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |full_adder|half_adder:inst1 ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version
    Info: Processing started: Tue Jun 25 02:45:32 2002
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off full_adder -c full_adder
Info: Found 2 design units, including 1 entities, in source file half_adder.vhd
    Info: Found design unit 1: half_adder-half_adder
    Info: Found entity 1: half_adder
Info: Found 1 design units, including 1 entities, in source file full_adder.bdf
    Info: Found entity 1: full_adder
Info: Elaborating entity "full_adder" for the top level hierarchy
Info: Elaborating entity "half_adder" for hierarchy "half_adder:inst1"
Info: Implemented 10 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 5 output pins
    Info: Implemented 2 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Allocated 159 megabytes of memory during processing
    Info: Processing ended: Tue Jun 25 02:45:38 2002
    Info: Elapsed time: 00:00:06