cheng4.vhd

用VHDL实现四位乘法器

LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cheng4 is
               port(
                      cin : IN STD_LOGIC;     
                      a : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
                      b : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
                    data_out: OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
end cheng4;
architecture one of cheng4 is
     signal t1: STD_LOGIC_VECTOR(4 DOWNTO 0);
     signal t2: STD_LOGIC_VECTOR(4 DOWNTO 0);
     signal t3: STD_LOGIC_VECTOR(4 DOWNTO 0);
     signal c0,c1,c2,c3:std_logic;
   COMPONENT  four_adder 
	    port(x3 : in STD_LOGIC;
		   x2 : in STD_LOGIC;
		   x1 : in STD_LOGIC;
		   cin : in STD_LOGIC;
		   s : out STD_LOGIC;
		   co : out STD_LOGIC);
    END COMPONENT;
    begin
    process (b,t1,t2,t3)
      begin
if b(0)='0' then  t1<="00000";
            else   t1(2 DOWNTO 0)<=a(2 DOWNTO 0); t1(4)<='0'; t1(3)<='0';
end if;
if b(1)='0' then  t2<="00000";
            else   t2(3 DOWNTO 1)<=a(2 DOWNTO 0); t2(4)<='0'; t2(0)<='0';
end if;
if b(2)='0' then  t3<="00000";
            else  t3(4 DOWNTO 2)<=a(2 DOWNTO 0); t3(1)<='0'; t3(0)<='0';
end if;
end process;
u1 : four_adder PORT MAP (x3=>t3(0),x2=>t2(0),x1=>t1(0),cin=>cin,s=>data_out(0),co=>c0);
u2 : four_adder PORT MAP (x3=>t3(1),x2=>t2(1),x1=>t1(1),cin=>c0,s=>data_out(1),co=>c1);
u3 : four_adder PORT MAP (x3=>t3(2),x2=>t2(2),x1=>t1(2),cin=>c1,s=>data_out(2),co=>c2);
u4 : four_adder PORT MAP (x3=>t3(3),x2=>t2(3),x1=>t1(3),cin=>c2,s=>data_out(3),co=>c3);
u5 : four_adder PORT MAP (x3=>t3(4),x2=>t2(4),x1=>t1(4),cin=>c3,s=>data_out(4),co=>data_out(5));  
end one;