four_adder.vhd

来自「用VHDL实现四位乘法器」· VHDL 代码 · 共 30 行

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity four_adder is
	    port(
		   x3 : in STD_LOGIC;
		   x2 : in STD_LOGIC;
		   x1 : in STD_LOGIC;
		   cin : in STD_LOGIC;
		   s : out STD_LOGIC;
		   co : out STD_LOGIC
	       );
end four_adder;
architecture one of four_adder is
begin
       co<=(x1 and cin and (not x3))or
           (x1 and x2 and (not cin)) or 
           (x1 and x3 and (not x2))or 
           (x3 and cin and (not x1))or 
           (x2 and cin and (not x1))or 
           (x2 and x3 and (not x1))  ;
       s<=( cin and (not x1)and (not x2)and (not x3)) or
          (x1 and (not cin)and (not x2)and (not x3)) or
          (x2 and (not x1)and (not cin)and (not x3))or 
          (cin and  x1 and  x2 and (not x3))or 
          (cin and  x3 and  x2 and (not x1))or 
          (x3 and  x1 and  x2 and (not cin))or
          (cin and  x1 and  x3 and (not x2))or 
          (x3 and (not x2)and (not x1)and (not cin));
end one;