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📄 spec.cpp

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💻 CPP
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////////////////////////////////////////////////////////////////////////////////
//   ____  ____   
//  /   /\/   /  
// /___/  \  /   
// \   \   \/  
//  \   \        Copyright (c) 2003-2004 Xilinx, Inc.
//  /   /        All Right Reserved. 
// /---/   /\     
// \   \  /  \  
//  \___\/\___\
////////////////////////////////////////////////////////////////////////////////

#include "work/spec/spec.h"
#include <stdarg.h>

#include "work/traffic_package/traffic_package.h"
#include "ieee/numeric_std/numeric_std.h"
#include "ieee/std_logic_unsigned/std_logic_unsigned.h"
#include "ieee/std_logic_1164/std_logic_1164.h"



static const HSim::LineNumberTable fileLineTable[] = {{0, 0}};

#include "isim/work/tlc_test_vhd/behavior.h"
extern HSim__s6* createWork_tlc_test_vhd_behavior(const char*);

static HSim__s6* IF2(
  HSim__s6* Arch,
  const char* label,
  int nGenerics,
  va_list vap)
{
    if (!label)
        label = "TLC_Test_vhd";
    HSim__s6* blk= createWork_tlc_test_vhd_behavior(label);
    return blk;
}


#include "work/traffic_package/traffic_package.h"
#include "ieee/std_logic_unsigned/std_logic_unsigned.h"
#include "ieee/std_logic_arith/std_logic_arith.h"
#include "ieee/std_logic_1164/std_logic_1164.h"
#include "isim/work/tlc_test_vhd/behavior.h"
static void GM2(Work_tlc_test_vhd_behavior* Arch,
  HSim__s6* inst,
  int nGenerics,
  va_list vap)
{
    const int64 * pCh = 0;
  if (--nGenerics >= 0) pCh = va_arg(vap, const int64 *);
int64 dvCh = 5000000LL;
    if (!pCh) { 
pCh = &dvCh;

}
    const int64 * pCk = 0;
  if (--nGenerics >= 0) pCk = va_arg(vap, const int64 *);
int64 dvCk = 2000000LL;
    if (!pCk) { 
pCk = &dvCk;

}
    inst->setGeneric("Long_time",(const char *)pCh, &HSimStandardPkg::Time);
    inst->setGeneric("Short_time",(const char *)pCk, &HSimStandardPkg::Time);
}

static void PM2(Work_tlc_test_vhd_behavior* Arch,
    HSim__s6* inst,
    int nPorts,
    va_list vap)
{
  HSimString lName;
    HSim__s1* pSn=0;
  if (--nPorts>=0) {
    lName=va_arg(vap,const char*);
    if (!lName.equal("Car_On_Farmroad"))
      globalKernel->error("Unexpected port name %s given for connection to %s.%s",lName,inst->getHierName(),"Car_On_Farmroad");
    pSn=va_arg(vap, HSim__s1 *);}
HSim__s1 & Sn=*pSn;
    HSim__s1* pSq=0;
  if (--nPorts>=0) {
    lName=va_arg(vap,const char*);
    if (!lName.equal("Highway_Light"))
      globalKernel->error("Unexpected port name %s given for connection to %s.%s",lName,inst->getHierName(),"Highway_Light");
    pSq=va_arg(vap, HSim__s1 *);}
HSim__s1 & Sq=*pSq;
    HSim__s1* pSs=0;
  if (--nPorts>=0) {
    lName=va_arg(vap,const char*);
    if (!lName.equal("Farmroad_Light"))
      globalKernel->error("Unexpected port name %s given for connection to %s.%s",lName,inst->getHierName(),"Farmroad_Light");
    pSs=va_arg(vap, HSim__s1 *);}
HSim__s1 & Ss=*pSs;
    inst->connectSig("Car_On_Farmroad",(&Sn));
    inst->connectSig("Highway_Light",(&Sq));
    inst->connectSig("Farmroad_Light",(&Ss));
}


extern HSim__s6* createWork_traffic_light_controller_behavioral(const char*);

#include "isim/work/tlc_test_vhd/behavior.h"
static HSim__s6* IF3(
  Work_tlc_test_vhd_behavior* Arch,
  const char* label,
  int nGenerics,
  va_list vap)
{
    if (!label)
        label = "Traffic_Light_Controller";
    HSim__s6* blk= createWork_traffic_light_controller_behavioral(label);
    return blk;
}


HSimConfigDecl *createWork_spec() {
  return new Work_spec();
}
Work_spec::Work_spec()
  : HSimConfigDecl("spec")
{
  HSimConfigDecl *cfg = 0;
    startBlock("behavior", IF2);
    startComp("Traffic_Light_Controller", HSimInstFactoryPtr(IF3), (HSimGenericMapPtr)GM2, (HSimPortMapPtr)PM2);
    compLabel("UUT");
    endComp("Traffic_Light_Controller");
    endBlock("behavior");
}

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