ibelieve.tan.qmsg

<I believe> song _verilog code for any device.

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "sys_clk " "Info: Assuming node \"sys_clk\" is an undefined clock" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 2 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "sys_clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "20 " "Warning: Found 20 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "divider\[13\] " "Info: Detected ripple clock \"divider\[13\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider\[13\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[12\] " "Info: Detected ripple clock \"divider\[12\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider\[12\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[11\] " "Info: Detected ripple clock \"divider\[11\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider\[11\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[10\] " "Info: Detected ripple clock \"divider\[10\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider\[10\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[9\] " "Info: Detected ripple clock \"divider\[9\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider\[9\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[8\] " "Info: Detected ripple clock \"divider\[8\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider\[8\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[7\] " "Info: Detected ripple clock \"divider\[7\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[6\] " "Info: Detected ripple clock \"divider\[6\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[5\] " "Info: Detected ripple clock \"divider\[5\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk_cnt\[23\] " "Info: Detected ripple clock \"clk_cnt\[23\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 9 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_cnt\[23\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[4\] " "Info: Detected ripple clock \"divider\[4\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[3\] " "Info: Detected ripple clock \"divider\[3\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[2\] " "Info: Detected ripple clock \"divider\[2\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Equal0~164 " "Info: Detected gated clock \"Equal0~164\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 19 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "Equal0~164" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Equal0~163 " "Info: Detected gated clock \"Equal0~163\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 19 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "Equal0~163" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Equal0~165 " "Info: Detected gated clock \"Equal0~165\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 19 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "Equal0~165" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Equal0~166 " "Info: Detected gated clock \"Equal0~166\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 19 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "Equal0~166" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[1\] " "Info: Detected ripple clock \"divider\[1\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk_cnt\[2\] " "Info: Detected ripple clock \"clk_cnt\[2\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 9 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_cnt\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[0\] " "Info: Detected ripple clock \"divider\[0\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "sys_clk register low\[0\] register origin\[1\] 171.61 MHz 5.827 ns Internal " "Info: Clock \"sys_clk\" has Internal fmax of 171.61 MHz between source register \"low\[0\]\" and destination register \"origin\[1\]\" (period= 5.827 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.587 ns + Longest register register " "Info: + Longest register to register delay is 5.587 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns low\[0\] 1 REG LC_X20_Y10_N3 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y10_N3; Fanout = 9; REG Node = 'low\[0\]'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { low[0] } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.348 ns) + CELL(0.442 ns) 1.790 ns Equal5~81 2 COMB LC_X20_Y14_N6 7 " "Info: 2: + IC(1.348 ns) + CELL(0.442 ns) = 1.790 ns; Loc. = LC_X20_Y14_N6; Fanout = 7; COMB Node = 'Equal5~81'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.790 ns" { low[0] Equal5~81 } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.809 ns) + CELL(0.590 ns) 3.189 ns WideNor0~62 3 COMB LC_X19_Y14_N7 3 " "Info: 3: + IC(0.809 ns) + CELL(0.590 ns) = 3.189 ns; Loc. = LC_X19_Y14_N7; Fanout = 3; COMB Node = 'WideNor0~62'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.399 ns" { Equal5~81 WideNor0~62 } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.226 ns) + CELL(0.442 ns) 4.857 ns WideNor0 4 COMB LC_X20_Y13_N1 1 " "Info: 4: + IC(1.226 ns) + CELL(0.442 ns) = 4.857 ns; Loc. = LC_X20_Y13_N1; Fanout = 1; COMB Node = 'WideNor0'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.668 ns" { WideNor0~62 WideNor0 } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.421 ns) + CELL(0.309 ns) 5.587 ns origin\[1\] 5 REG LC_X20_Y13_N0 1 " "Info: 5: + IC(0.421 ns) + CELL(0.309 ns) = 5.587 ns; Loc. = LC_X20_Y13_N0; Fanout = 1; REG Node = 'origin\[1\]'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.730 ns" { WideNor0 origin[1] } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.783 ns ( 31.91 % ) " "Info: Total cell delay = 1.783 ns ( 31.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.804 ns ( 68.09 % ) " "Info: Total interconnect delay = 3.804 ns ( 68.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.587 ns" { low[0] Equal5~81 WideNor0~62 WideNor0 origin[1] } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "5.587 ns" { low[0] {} Equal5~81 {} WideNor0~62 {} WideNor0 {} origin[1] {} } { 0.000ns 1.348ns 0.809ns 1.226ns 0.421ns } { 0.000ns 0.442ns 0.590ns 0.442ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.021 ns - Smallest " "Info: - Smallest clock skew is 0.021 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clk destination 7.408 ns + Shortest register " "Info: + Shortest clock path from clock \"sys_clk\" to destination register is 7.408 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sys_clk 1 CLK PIN_153 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 24; CLK Node = 'sys_clk'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sys_clk } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns clk_cnt\[23\] 2 REG LC_X8_Y10_N6 26 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N6; Fanout = 26; REG Node = 'clk_cnt\[23\]'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { sys_clk clk_cnt[23] } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.548 ns) + CELL(0.711 ns) 7.408 ns origin\[1\] 3 REG LC_X20_Y13_N0 1 " "Info: 3: + IC(3.548 ns) + CELL(0.711 ns) = 7.408 ns; Loc. = LC_X20_Y13_N0; Fanout = 1; REG Node = 'origin\[1\]'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.259 ns" { clk_cnt[23] origin[1] } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.05 % ) " "Info: Total cell delay = 3.115 ns ( 42.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.293 ns ( 57.95 % ) " "Info: Total interconnect delay = 4.293 ns ( 57.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "7.408 ns" { sys_clk clk_cnt[23] origin[1] } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "7.408 ns" { sys_clk {} sys_clk~out0 {} clk_cnt[23] {} origin[1] {} } { 0.000ns 0.000ns 0.745ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clk source 7.387 ns - Longest register " "Info: - Longest clock path from clock \"sys_clk\" to source register is 7.387 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sys_clk 1 CLK PIN_153 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 24; CLK Node = 'sys_clk'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sys_clk } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns clk_cnt\[23\] 2 REG LC_X8_Y10_N6 26 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N6; Fanout = 26; REG Node = 'clk_cnt\[23\]'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { sys_clk clk_cnt[23] } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.527 ns) + CELL(0.711 ns) 7.387 ns low\[0\] 3 REG LC_X20_Y10_N3 9 " "Info: 3: + IC(3.527 ns) + CELL(0.711 ns) = 7.387 ns; Loc. = LC_X20_Y10_N3; Fanout = 9; REG Node = 'low\[0\]'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.238 ns" { clk_cnt[23] low[0] } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.17 % ) " "Info: Total cell delay = 3.115 ns ( 42.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.272 ns ( 57.83 % ) " "Info: Total interconnect delay = 4.272 ns ( 57.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "7.387 ns" { sys_clk clk_cnt[23] low[0] } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "7.387 ns" { sys_clk {} sys_clk~out0 {} clk_cnt[23] {} low[0] {} } { 0.000ns 0.000ns 0.745ns 3.527ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "7.408 ns" { sys_clk clk_cnt[23] origin[1] } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "7.408 ns" { sys_clk {} sys_clk~out0 {} clk_cnt[23] {} origin[1] {} } { 0.000ns 0.000ns 0.745ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "7.387 ns" { sys_clk clk_cnt[23] low[0] } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "7.387 ns" { sys_clk {} sys_clk~out0 {} clk_cnt[23] {} low[0] {} } { 0.000ns 0.000ns 0.745ns 3.527ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 53 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 35 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.587 ns" { low[0] Equal5~81 WideNor0~62 WideNor0 origin[1] } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "5.587 ns" { low[0] {} Equal5~81 {} WideNor0~62 {} WideNor0 {} origin[1] {} } { 0.000ns 1.348ns 0.809ns 1.226ns 0.421ns } { 0.000ns 0.442ns 0.590ns 0.442ns 0.309ns } "" } } { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "7.408 ns" { sys_clk clk_cnt[23] origin[1] } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "7.408 ns" { sys_clk {} sys_clk~out0 {} clk_cnt[23] {} origin[1] {} } { 0.000ns 0.000ns 0.745ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "7.387 ns" { sys_clk clk_cnt[23] low[0] } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "7.387 ns" { sys_clk {} sys_clk~out0 {} clk_cnt[23] {} low[0] {} } { 0.000ns 0.000ns 0.745ns 3.527ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}