ibelieve.tan.qmsg

来自「<I believe> song _verilog code for」· QMSG 代码 · 共 9 行 · 第 1/3 页

{ "Info" "ITDB_FULL_TCO_RESULT" "sys_clk sp sp~reg0 18.557 ns register " "Info: tco from clock \"sys_clk\" to destination pin \"sp\" through register \"sp~reg0\" is 18.557 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clk source 12.168 ns + Longest register " "Info: + Longest clock path from clock \"sys_clk\" to source register is 12.168 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sys_clk 1 CLK PIN_153 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 24; CLK Node = 'sys_clk'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sys_clk } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns clk_cnt\[2\] 2 REG LC_X8_Y12_N5 17 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y12_N5; Fanout = 17; REG Node = 'clk_cnt\[2\]'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { sys_clk clk_cnt[2] } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.304 ns) + CELL(0.935 ns) 8.388 ns divider\[3\] 3 REG LC_X20_Y13_N6 4 " "Info: 3: + IC(4.304 ns) + CELL(0.935 ns) = 8.388 ns; Loc. = LC_X20_Y13_N6; Fanout = 4; REG Node = 'divider\[3\]'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.239 ns" { clk_cnt[2] divider[3] } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.280 ns) + CELL(0.590 ns) 10.258 ns Equal0~163 4 COMB LC_X21_Y12_N2 1 " "Info: 4: + IC(1.280 ns) + CELL(0.590 ns) = 10.258 ns; Loc. = LC_X21_Y12_N2; Fanout = 1; COMB Node = 'Equal0~163'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.870 ns" { divider[3] Equal0~163 } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.450 ns) + CELL(0.292 ns) 11.000 ns Equal0 5 COMB LC_X21_Y12_N6 15 " "Info: 5: + IC(0.450 ns) + CELL(0.292 ns) = 11.000 ns; Loc. = LC_X21_Y12_N6; Fanout = 15; COMB Node = 'Equal0'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.742 ns" { Equal0~163 Equal0 } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.457 ns) + CELL(0.711 ns) 12.168 ns sp~reg0 6 REG LC_X21_Y12_N9 2 " "Info: 6: + IC(0.457 ns) + CELL(0.711 ns) = 12.168 ns; Loc. = LC_X21_Y12_N9; Fanout = 2; REG Node = 'sp~reg0'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.168 ns" { Equal0 sp~reg0 } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 29 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.932 ns ( 40.53 % ) " "Info: Total cell delay = 4.932 ns ( 40.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.236 ns ( 59.47 % ) " "Info: Total interconnect delay = 7.236 ns ( 59.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "12.168 ns" { sys_clk clk_cnt[2] divider[3] Equal0~163 Equal0 sp~reg0 } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "12.168 ns" { sys_clk {} sys_clk~out0 {} clk_cnt[2] {} divider[3] {} Equal0~163 {} Equal0 {} sp~reg0 {} } { 0.000ns 0.000ns 0.745ns 4.304ns 1.280ns 0.450ns 0.457ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.292ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 29 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.165 ns + Longest register pin " "Info: + Longest register to pin delay is 6.165 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sp~reg0 1 REG LC_X21_Y12_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y12_N9; Fanout = 2; REG Node = 'sp~reg0'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sp~reg0 } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 29 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.057 ns) + CELL(2.108 ns) 6.165 ns sp 2 PIN PIN_62 0 " "Info: 2: + IC(4.057 ns) + CELL(2.108 ns) = 6.165 ns; Loc. = PIN_62; Fanout = 0; PIN Node = 'sp'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "6.165 ns" { sp~reg0 sp } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 34.19 % ) " "Info: Total cell delay = 2.108 ns ( 34.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.057 ns ( 65.81 % ) " "Info: Total interconnect delay = 4.057 ns ( 65.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "6.165 ns" { sp~reg0 sp } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "6.165 ns" { sp~reg0 {} sp {} } { 0.000ns 4.057ns } { 0.000ns 2.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "12.168 ns" { sys_clk clk_cnt[2] divider[3] Equal0~163 Equal0 sp~reg0 } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "12.168 ns" { sys_clk {} sys_clk~out0 {} clk_cnt[2] {} divider[3] {} Equal0~163 {} Equal0 {} sp~reg0 {} } { 0.000ns 0.000ns 0.745ns 4.304ns 1.280ns 0.450ns 0.457ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.292ns 0.711ns } "" } } { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "6.165 ns" { sp~reg0 sp } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "6.165 ns" { sp~reg0 {} sp {} } { 0.000ns 4.057ns } { 0.000ns 2.108ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "111 " "Info: Allocated 111 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 16 11:00:51 2008 " "Info: Processing ended: Wed Jul 16 11:00:51 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}