niosii_c.v

nios num clock verilog code

                                     cpu_data_master_read_data_valid_uart_s1,
                                     cpu_data_master_requests_button_pio_s1,
                                     cpu_data_master_requests_cpu_jtag_debug_module,
                                     cpu_data_master_requests_ext_flash_s1,
                                     cpu_data_master_requests_jtag_uart_avalon_jtag_slave,
                                     cpu_data_master_requests_lcd_16207_0_control_slave,
                                     cpu_data_master_requests_led_pio_s1,
                                     cpu_data_master_requests_onchip_ram_4K_s1,
                                     cpu_data_master_requests_sdram_s1,
                                     cpu_data_master_requests_sysid_control_slave,
                                     cpu_data_master_requests_sysy_clk_timer_s1,
                                     cpu_data_master_requests_uart_s1,
                                     cpu_data_master_write,
                                     cpu_data_master_writedata,
                                     cpu_jtag_debug_module_readdata_from_sa,
                                     d1_button_pio_s1_end_xfer,
                                     d1_cpu_jtag_debug_module_end_xfer,
                                     d1_ext_bus_avalon_slave_end_xfer,
                                     d1_jtag_uart_avalon_jtag_slave_end_xfer,
                                     d1_lcd_16207_0_control_slave_end_xfer,
                                     d1_led_pio_s1_end_xfer,
                                     d1_onchip_ram_4K_s1_end_xfer,
                                     d1_sdram_s1_end_xfer,
                                     d1_sysid_control_slave_end_xfer,
                                     d1_sysy_clk_timer_s1_end_xfer,
                                     d1_uart_s1_end_xfer,
                                     ext_flash_s1_wait_counter_eq_0,
                                     ext_flash_s1_wait_counter_eq_1,
                                     incoming_ext_bus_data_with_Xs_converted_to_0,
                                     jtag_uart_avalon_jtag_slave_irq_from_sa,
                                     jtag_uart_avalon_jtag_slave_readdata_from_sa,
                                     jtag_uart_avalon_jtag_slave_waitrequest_from_sa,
                                     lcd_16207_0_control_slave_readdata_from_sa,
                                     lcd_16207_0_control_slave_wait_counter_eq_0,
                                     lcd_16207_0_control_slave_wait_counter_eq_1,
                                     onchip_ram_4K_s1_posted_fifo_readenable,
                                     onchip_ram_4K_s1_posted_fifo_writenable,
                                     onchip_ram_4K_s1_readdata_from_sa,
                                     onchip_ram_4K_s1_waitrequest_from_sa,
                                     registered_cpu_data_master_read_data_valid_ext_flash_s1,
                                     reset_n,
                                     sdram_s1_posted_fifo_readenable,
                                     sdram_s1_posted_fifo_writenable,
                                     sdram_s1_readdata_from_sa,
                                     sdram_s1_waitrequest_from_sa,
                                     sysid_control_slave_readdata_from_sa,
                                     sysy_clk_timer_s1_irq_from_sa,
                                     sysy_clk_timer_s1_readdata_from_sa,
                                     uart_s1_irq_from_sa,
                                     uart_s1_readdata_from_sa,

                                    // outputs:
                                     cpu_data_master_address_to_slave,
                                     cpu_data_master_dbs_address,
                                     cpu_data_master_dbs_write_16,
                                     cpu_data_master_irq,
                                     cpu_data_master_no_byte_enables_and_last_term,
                                     cpu_data_master_readdata,
                                     cpu_data_master_waitrequest
                                  );

  output  [ 25: 0] cpu_data_master_address_to_slave;
  output  [  1: 0] cpu_data_master_dbs_address;
  output  [ 15: 0] cpu_data_master_dbs_write_16;
  output  [ 31: 0] cpu_data_master_irq;
  output           cpu_data_master_no_byte_enables_and_last_term;
  output  [ 31: 0] cpu_data_master_readdata;
  output           cpu_data_master_waitrequest;
  input            button_pio_s1_irq_from_sa;
  input   [  3: 0] button_pio_s1_readdata_from_sa;
  input            clk;
  input   [ 25: 0] cpu_data_master_address;
  input   [  1: 0] cpu_data_master_byteenable_ext_flash_s1;
  input            cpu_data_master_debugaccess;
  input            cpu_data_master_granted_button_pio_s1;
  input            cpu_data_master_granted_cpu_jtag_debug_module;
  input            cpu_data_master_granted_ext_flash_s1;
  input            cpu_data_master_granted_jtag_uart_avalon_jtag_slave;
  input            cpu_data_master_granted_lcd_16207_0_control_slave;
  input            cpu_data_master_granted_led_pio_s1;
  input            cpu_data_master_granted_onchip_ram_4K_s1;
  input            cpu_data_master_granted_sdram_s1;
  input            cpu_data_master_granted_sysid_control_slave;
  input            cpu_data_master_granted_sysy_clk_timer_s1;
  input            cpu_data_master_granted_uart_s1;
  input            cpu_data_master_qualified_request_button_pio_s1;
  input            cpu_data_master_qualified_request_cpu_jtag_debug_module;
  input            cpu_data_master_qualified_request_ext_flash_s1;
  input            cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
  input            cpu_data_master_qualified_request_lcd_16207_0_control_slave;
  input            cpu_data_master_qualified_request_led_pio_s1;
  input            cpu_data_master_qualified_request_onchip_ram_4K_s1;
  input            cpu_data_master_qualified_request_sdram_s1;
  input            cpu_data_master_qualified_request_sysid_control_slave;
  input            cpu_data_master_qualified_request_sysy_clk_timer_s1;
  input            cpu_data_master_qualified_request_uart_s1;
  input            cpu_data_master_read;
  input            cpu_data_master_read_data_valid_button_pio_s1;
  input            cpu_data_master_read_data_valid_cpu_jtag_debug_module;
  input            cpu_data_master_read_data_valid_ext_flash_s1;
  input            cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave;
  input            cpu_data_master_read_data_valid_lcd_16207_0_control_slave;
  input            cpu_data_master_read_data_valid_led_pio_s1;
  input            cpu_data_master_read_data_valid_onchip_ram_4K_s1;
  input   [  6: 0] cpu_data_master_read_data_valid_onchip_ram_4K_s1_shift_register;
  input            cpu_data_master_read_data_valid_sdram_s1;
  input   [  6: 0] cpu_data_master_read_data_valid_sdram_s1_shift_register;
  input            cpu_data_master_read_data_valid_sysid_control_slave;
  input            cpu_data_master_read_data_valid_sysy_clk_timer_s1;
  input            cpu_data_master_read_data_valid_uart_s1;
  input            cpu_data_master_requests_button_pio_s1;
  input            cpu_data_master_requests_cpu_jtag_debug_module;
  input            cpu_data_master_requests_ext_flash_s1;
  input            cpu_data_master_requests_jtag_uart_avalon_jtag_slave;
  input            cpu_data_master_requests_lcd_16207_0_control_slave;
  input            cpu_data_master_requests_led_pio_s1;
  input            cpu_data_master_requests_onchip_ram_4K_s1;
  input            cpu_data_master_requests_sdram_s1;
  input            cpu_data_master_requests_sysid_control_slave;
  input            cpu_data_master_requests_sysy_clk_timer_s1;
  input            cpu_data_master_requests_uart_s1;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input   [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
  input            d1_button_pio_s1_end_xfer;
  input            d1_cpu_jtag_debug_module_end_xfer;
  input            d1_ext_bus_avalon_slave_end_xfer;
  input            d1_jtag_uart_avalon_jtag_slave_end_xfer;
  input            d1_lcd_16207_0_control_slave_end_xfer;
  input            d1_led_pio_s1_end_xfer;
  input            d1_onchip_ram_4K_s1_end_xfer;
  input            d1_sdram_s1_end_xfer;
  input            d1_sysid_control_slave_end_xfer;
  input            d1_sysy_clk_timer_s1_end_xfer;
  input            d1_uart_s1_end_xfer;
  input            ext_flash_s1_wait_counter_eq_0;
  input            ext_flash_s1_wait_counter_eq_1;
  input   [ 15: 0] incoming_ext_bus_data_with_Xs_converted_to_0;
  input            jtag_uart_avalon_jtag_slave_irq_from_sa;
  input   [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa;
  input            jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
  input   [  7: 0] lcd_16207_0_control_slave_readdata_from_sa;
  input            lcd_16207_0_control_slave_wait_counter_eq_0;
  input            lcd_16207_0_control_slave_wait_counter_eq_1;
  input   [  6: 0] onchip_ram_4K_s1_posted_fifo_readenable;
  input   [  6: 0] onchip_ram_4K_s1_posted_fifo_writenable;
  input   [ 31: 0] onchip_ram_4K_s1_readdata_from_sa;
  input            onchip_ram_4K_s1_waitrequest_from_sa;
  input            registered_cpu_data_master_read_data_valid_ext_flash_s1;
  input            reset_n;
  input   [  6: 0] sdram_s1_posted_fifo_readenable;
  input   [  6: 0] sdram_s1_posted_fifo_writenable;
  input   [ 31: 0] sdram_s1_readdata_from_sa;
  input            sdram_s1_waitrequest_from_sa;
  input   [ 31: 0] sysid_control_slave_readdata_from_sa;
  input            sysy_clk_timer_s1_irq_from_sa;
  input   [ 15: 0] sysy_clk_timer_s1_readdata_from_sa;
  input            uart_s1_irq_from_sa;
  input   [ 15: 0] uart_s1_readdata_from_sa;

  wire    [ 25: 0] cpu_data_master_address_to_slave;
  reg     [  1: 0] cpu_data_master_dbs_address;
  wire    [  1: 0] cpu_data_master_dbs_increment;
  wire    [ 15: 0] cpu_data_master_dbs_write_16;
  wire    [ 31: 0] cpu_data_master_irq;
  reg              cpu_data_master_no_byte_enables_and_last_term;
  wire    [ 31: 0] cpu_data_master_readdata;
  wire             cpu_data_master_run;
  reg              cpu_data_master_waitrequest;
  reg     [ 15: 0] dbs_16_reg_segment_0;
  wire             dbs_count_enable;
  wire             dbs_counter_overflow;
  wire             dummy_sink;
  wire             last_dbs_term_and_run;
  wire    [  1: 0] next_dbs_address;
  wire    [ 15: 0] p1_dbs_16_reg_segment_0;
  wire    [ 31: 0] p1_registered_cpu_data_master_readdata;
  wire             pre_dbs_count_enable;
  wire             r_0;
  wire             r_1;
  wire             r_2;
  reg     [ 31: 0] registered_cpu_data_master_readdata;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (cpu_data_master_qualified_request_button_pio_s1 | ~cpu_data_master_requests_button_pio_s1) & ((~cpu_data_master_qualified_request_button_pio_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_button_pio_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_cpu_jtag_debug_module | ~cpu_data_master_requests_cpu_jtag_debug_module) & (cpu_data_master_granted_cpu_jtag_debug_module | ~cpu_data_master_qualified_request_cpu_jtag_debug_module) & ((~cpu_data_master_qualified_request_cpu_jtag_debug_module | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_cpu_jtag_debug_module | ~cpu_data_master_write | (1 & 1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_ext_flash_s1 | (registered_cpu_data_master_read_data_valid_ext_flash_s1 & cpu_data_master_dbs_address[1]) | (cpu_data_master_write & !cpu_data_master_byteenable_ext_flash_s1 & cpu_data_master_dbs_address[1]) | ~cpu_data_master_requests_ext_flash_s1) & (cpu_data_master_granted_ext_flash_s1 | ~cpu_data_master_qualified_request_ext_flash_s1) & ((~cpu_data_master_qualified_request_ext_flash_s1 | ~cpu_data_master_read | (registered_cpu_data_master_read_data_valid_ext_flash_s1 & (cpu_data_master_dbs_address[1]) & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_ext_flash_s1 | ~cpu_data_master_write | (1 & ext_flash_s1_wait_counter_eq_1 & (cpu_data_master_dbs_address[1]) & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~cpu_data_master_requests_jtag_uart_avalon_jtag_slave) & ((~cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~cpu_data_master_read | (1 & ~jtag_uart_avalon_jtag_slave_waitrequest_from_sa & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~cpu_data_master_write | (1 & ~jtag_uart_avalon_jtag_slave_waitrequest_from_sa & cpu_data_master_write))) & 1 & ((~cpu_data_master_qualified_request_lcd_16207_0_control_slave | ~cpu_data_master_read | (1 & lcd_16207_0_control_slave_wait_counter_eq_1 & cpu_data_master_read)));

  //cascaded wait assignment, which is an e_assign
  assign cpu_data_master_run = r_0 & r_1 & r_2;

  //r_1 master_run cascaded wait assignment, which is an e_assign
  assign r_1 = ((~cpu_data_master_qualified_request_lcd_16207_0_control_slave | ~cpu_data_master_write | (1 & lcd_16207_0_control_slave_wait_counter_eq_1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_led_pio_s1 | ~cpu_data_master_requests_led_pio_s1) & ((~cpu_data_master_qualified_request_led_pio_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_led_pio_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_onchip_ram_4K_s1 | cpu_data_master_read_data_valid_onchip_ram_4K_s1 | ~cpu_data_master_requests_onchip_ram_4K_s1) & (cpu_data_master_granted_onchip_ram_4K_s1 | ~cpu_data_master_qualified_request_onchip_ram_4K_s1) & ((~cpu_data_master_qualified_request_onchip_ram_4K_s1 | ~cpu_data_master_read | (cpu_data_master_read_data_valid_onchip_ram_4K_s1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_onchip_ram_4K_s1 | ~cpu_data_master_write | (1 & ~onchip_ram_4K_s1_waitrequest_from_sa & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_sdram_s1 | cpu_data_master_read_data_valid_sdram_s1 | ~cpu_data_master_requests_sdram_s1) & (cpu_data_master_granted_sdram_s1 | ~cpu_data_master_qualified_request_sdram_s1) & ((~cpu_data_master_qualified_request_sdram_s1 | ~cpu_data_master_read | (cpu_data_master_read_data_valid_sdram_s1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_sdram_s1 | ~cpu_data_master_write | (1 & ~sdram_s1_waitrequest_from_sa & cpu_data_master_write))) & 1 & ((~cpu_data_master_qualified_request_sysid_control_slave | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_sysid_control_slave | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_sysy_clk_timer_s1 | ~cpu_data_master_requests_sysy_clk_timer_s1);

  //r_2 master_run cascaded wait assignment, which is an e_assign
  assign r_2 = ((~cpu_data_master_qualified_request_sysy_clk_timer_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_sysy_clk_timer_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & ((~cpu_data_master_qualified_request_uart_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_uart_s1 | ~cpu_data_master_write | (1 & 1 & cpu_data_master_write)));

  //optimize select-logic by passing only those address bits which matter.
  assign cpu_data_master_address_to_slave = cpu_data_master_address[25 : 0];

  //cpu/data_master readdata mux, which is an e_mux
  assign cpu_data_master_readdata = ({32 {~cpu_data_master_requests_button_pio_s1}} | button_pio_s1_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_cpu_jtag_debug_module}} | cpu_jtag_debug_module_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_ext_flash_s1}} | {incoming_ext_bus_data_with_Xs_converted_to_0,
    dbs_16_reg_segment_0}) &
    ({32 {~cpu_data_master_requests_jtag_uart_avalon_jtag_slave}} | registered_cpu_data_master_readdata) &
    ({32 {~cpu_data_master_requests_lcd_16207_0_control_slave}} | lcd_16207_0_control_slave_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_onchip_ram_4K_s1}} | registered_cpu_data_master_readdata) &
    ({32 {~cpu_data_master_requests_sdram_s1}} | registered_cpu_data_master_readdata) &
    ({32 {~cpu_data_master_requests_sysid_control_slave}} | sysid_control_slave_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_sysy_clk_timer_s1}} | sysy_clk_timer_s1_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_uart_s1}} | uart_s1_readdata_from_sa);

  //actual waitrequest port, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_data_master_waitrequest <= ~0;
      else if (1)
          cpu_data_master_waitrequest <= ~((~(cpu_data_master_read | cpu_data_master_write))? 0: (cpu_data_master_run & cpu_data_master_waitrequest));
    end