niosii_c.ptf

nios num clock verilog code

               comment = "Log2 size in bytes of each dcache line";
            }
         }
         license_status = "encrypted";
         germs_monitor_id = "";
         mainmem_slave = "onchip_ram_4K/s1";
         datamem_slave = "onchip_ram_4K/s1";
         maincomm_slave = "lcd_16207_0/control_slave";
         cpuid_sz = "1";
         cpuid_value = "0";
      }
      SYSTEM_BUILDER_INFO 
      {
         Parameters_Signature = "";
         Is_CPU = "1";
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Required_Device_Family = "STRATIX,STRATIXII,CYCLONE,CYCLONEII";
         Default_Module_Name = "cpu";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "clk";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
            Settings_Summary = "Nios II/e
            
            
            <br>&nbsp;&nbsp;JTAG Debug Module
            ";
         }
      }
      PORT_WIRING 
      {
         PORT jtag_debug_trigout
         {
            Is_Enabled = "0";
         }
         PORT jtag_debug_offchip_trace_clk
         {
            Is_Enabled = "0";
         }
         PORT jtag_debug_offchip_trace_data
         {
            Is_Enabled = "0";
         }
      }
      SOFTWARE_COMPONENT altera_plugs_library
      {
         class = "altera_plugs_library";
         class_version = "2.1";
         WIZARD_SCRIPT_ARGUMENTS 
         {
            CONSTANTS 
            {
               CONSTANT PLUGS_PLUG_COUNT
               {
                  value = "5";
                  comment = "Maximum number of plugs";
               }
               CONSTANT PLUGS_ADAPTER_COUNT
               {
                  value = "2";
                  comment = "Maximum number of adapters";
               }
               CONSTANT PLUGS_DNS
               {
                  value = "1";
                  comment = "Have routines for DNS lookups";
               }
               CONSTANT PLUGS_PING
               {
                  value = "1";
                  comment = "Respond to icmp echo (ping) messages";
               }
               CONSTANT PLUGS_TCP
               {
                  value = "1";
                  comment = "Support tcp in/out connections";
               }
               CONSTANT PLUGS_IRQ
               {
                  value = "1";
                  comment = "Run at interrupte level";
               }
               CONSTANT PLUGS_DEBUG
               {
                  value = "1";
                  comment = "Support debug routines";
               }
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Is_Enabled = "1";
         }
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL aaa
            {
               format = "Logic";
               name = "d_irq";
               radix = "hexadecimal";
            }
            SIGNAL aab
            {
               format = "Logic";
               name = "d_waitrequest";
               radix = "hexadecimal";
            }
            SIGNAL aac
            {
               format = "Logic";
               name = "d_address";
               radix = "hexadecimal";
            }
            SIGNAL aad
            {
               format = "Logic";
               name = "d_byteenable";
               radix = "hexadecimal";
            }
            SIGNAL aae
            {
               format = "Logic";
               name = "d_read";
               radix = "hexadecimal";
            }
            SIGNAL aaf
            {
               format = "Logic";
               name = "d_readdata";
               radix = "hexadecimal";
            }
            SIGNAL aag
            {
               format = "Logic";
               name = "d_write";
               radix = "hexadecimal";
            }
            SIGNAL aah
            {
               format = "Logic";
               name = "d_writedata";
               radix = "hexadecimal";
            }
            SIGNAL aai
            {
               format = "Logic";
               name = "i_waitrequest";
               radix = "hexadecimal";
            }
            SIGNAL aaj
            {
               format = "Logic";
               name = "i_address";
               radix = "hexadecimal";
            }
            SIGNAL aak
            {
               format = "Logic";
               name = "i_read";
               radix = "hexadecimal";
            }
            SIGNAL aal
            {
               format = "Logic";
               name = "i_readdata";
               radix = "hexadecimal";
            }
            SIGNAL aam
            {
               format = "Logic";
               name = "the_cpu_test_bench/F_pcb";
               radix = "hexadecimal";
            }
            SIGNAL aan
            {
               format = "Logic";
               name = "the_cpu_test_bench/W_vinst";
               radix = "ascii";
            }
            SIGNAL aao
            {
               format = "Logic";
               name = "the_cpu_test_bench/W_valid";
               radix = "hexadecimal";
            }
            SIGNAL aap
            {
               format = "Logic";
               name = "the_cpu_test_bench/D_iw";
               radix = "hexadecimal";
            }
         }
      }
   }
   MODULE sysy_clk_timer
   {
      class = "altera_avalon_timer";
      class_version = "2.1";
      iss_model_name = "altera_avalon_timer";
      SLAVE s1
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Address_Width = "3";
            Data_Width = "16";
            Has_IRQ = "1";
            Read_Wait_States = "1";
            Write_Wait_States = "0";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "0";
            }
            Base_Address = "0x00000800";
         }
         PORT_WIRING 
         {
            PORT address
            {
               Is_Enabled = "1";
               direction = "input";
               type = "address";
               width = "3";
            }
            PORT chipselect
            {
               Is_Enabled = "1";
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT irq
            {
               Is_Enabled = "1";
               direction = "output";
               type = "irq";
               width = "1";
            }
            PORT readdata
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readdata";
               width = "16";
            }
            PORT reset_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
            PORT write_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "write_n";
               width = "1";
            }
            PORT writedata
            {
               Is_Enabled = "1";
               direction = "input";
               type = "writedata";
               width = "16";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Clock_Source = "clk";
         View 
         {
            Settings_Summary = "Timer with 1 ms timeout period.";
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         always_run = "1";
         fixed_period = "1";
         snapshot = "0";
         period = "1";
         period_units = "ms";
         reset_output = "0";
         timeout_pulse_output = "0";
         mult = "0.001";
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sysy_clk_timer.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
      }
   }
   MODULE led_pio
   {
      class = "altera_avalon_pio";
      class_version = "2.2";
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/led_pio.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
         PORT in_port
         {
            direction = "input";
            Is_Enabled = "0";
            width = "4";
         }
         PORT out_port
         {
            direction = "output";
            Is_Enabled = "1";
            width = "4";
         }
         PORT bidir_port
         {
            direction = "inout";
            Is_Enabled = "0";
            width = "4";
         }
      }
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT address
            {
               Is_Enabled = "1";
               direction = "input";
               type = "address";
               width = "2";
            }
            PORT chipselect
            {
               Is_Enabled = "1";
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT reset_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
            PORT write_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "write_n";
               width = "1";
            }
            PORT writedata
            {
               Is_Enabled = "1";
               direction = "input";
               type = "writedata";
               width = "4";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Has_IRQ = "0";
            Address_Width = "2";
            Data_Width = "4";
            Base_Address = "0x00000840";
            Address_Alignment = "native";
            Read_Wait_States = "1";
            Write_Wait_States = "0";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Date_Modified = "";
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Wire_Test_Bench_Values = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "clk";
         View 
         {
            Settings_Summary = " 4-bit PIO using <br>
					
					
					 output pins";
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Do_Test_Bench_Wiring = "0";
         Driven_Sim_Value = "0x0000";
         has_tri = "0";
         has_out = "1";
         has_in = "0";
         capture = "0";
         edge_type = "NONE";
         irq_type = "NONE";
      }
   }
   MODULE button_pio
   {
      class = "altera_avalon_pio";
      class_version = "2.2";