niosii_c.ptf

nios num clock verilog code

         Fix_Me_Up = "";
         DISPLAY 
         {
            SIGNAL a
            {
               name = "az_addr";
               radix = "hexadecimal";
            }
            SIGNAL b
            {
               name = "az_be_n";
               radix = "hexadecimal";
            }
            SIGNAL c
            {
               name = "az_cs";
            }
            SIGNAL d
            {
               name = "az_data";
               radix = "hexadecimal";
            }
            SIGNAL e
            {
               name = "az_rd_n";
            }
            SIGNAL f
            {
               name = "az_wr_n";
            }
            SIGNAL g
            {
               name = "clk";
            }
            SIGNAL h
            {
               name = "za_data";
               radix = "hexadecimal";
            }
            SIGNAL i
            {
               name = "za_valid";
            }
            SIGNAL j
            {
               name = "za_waitrequest";
            }
            SIGNAL k
            {
               name = "za_cannotrefresh";
               suppress = "1";
            }
            SIGNAL l
            {
               name = "CODE";
               radix = "ascii";
            }
            SIGNAL m
            {
               name = "zs_addr";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL n
            {
               name = "zs_ba";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL o
            {
               name = "zs_cs_n";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL p
            {
               name = "zs_ras_n";
               suppress = "0";
            }
            SIGNAL q
            {
               name = "zs_cas_n";
               suppress = "0";
            }
            SIGNAL r
            {
               name = "zs_we_n";
               suppress = "0";
            }
            SIGNAL s
            {
               name = "zs_dq";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL t
            {
               name = "zs_dqm";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL u
            {
               name = "zt_addr";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL v
            {
               name = "zt_ba";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL w
            {
               name = "zt_oe";
               suppress = "1";
            }
            SIGNAL x
            {
               name = "zt_cke";
               suppress = "1";
            }
            SIGNAL y
            {
               name = "zt_chipselect";
               suppress = "1";
            }
            SIGNAL z0
            {
               name = "zt_lock_n";
               suppress = "1";
            }
            SIGNAL z1
            {
               name = "zt_ras_n";
               suppress = "1";
            }
            SIGNAL z2
            {
               name = "zt_cas_n";
               suppress = "1";
            }
            SIGNAL z3
            {
               name = "zt_we_n";
               suppress = "1";
            }
            SIGNAL z4
            {
               name = "zt_cs_n";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL z5
            {
               name = "zt_dqm";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL z6
            {
               name = "zt_data";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL z7
            {
               name = "tz_data";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL z8
            {
               name = "tz_waitrequest";
               suppress = "1";
            }
         }
         PORT_WIRING 
         {
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               width = "1";
            }
            PORT zs_addr
            {
               Is_Enabled = "1";
               direction = "input";
               width = "12";
            }
            PORT zs_ba
            {
               Is_Enabled = "1";
               direction = "input";
               width = "2";
            }
            PORT zs_cas_n
            {
               Is_Enabled = "1";
               direction = "input";
               width = "1";
            }
            PORT zs_cke
            {
               Is_Enabled = "1";
               direction = "input";
               width = "1";
            }
            PORT zs_cs_n
            {
               Is_Enabled = "1";
               direction = "input";
               width = "1";
            }
            PORT zs_dq
            {
               Is_Enabled = "1";
               direction = "inout";
               width = "32";
            }
            PORT zs_dqm
            {
               Is_Enabled = "1";
               direction = "input";
               width = "4";
            }
            PORT zs_ras_n
            {
               Is_Enabled = "1";
               direction = "input";
               width = "1";
            }
            PORT zs_we_n
            {
               Is_Enabled = "1";
               direction = "input";
               width = "1";
            }
         }
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/onchip_ram_4K.v, __PROJECT_DIRECTORY__/onchip_ram_4K_test_component.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
      }
   }
   MODULE cpu
   {
      class = "altera_nios2";
      class_version = "5.0";
      iss_model_name = "altera_nios2";
      HDL_INFO 
      {
         PLI_Files = "";
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/cpu_test_bench.v, __PROJECT_DIRECTORY__/cpu_jtag_debug_module.v, __PROJECT_DIRECTORY__/cpu_jtag_debug_module_wrapper.v, __PROJECT_DIRECTORY__/cpu.vo";
         Synthesis_Only_Files = "";
      }
      MASTER instruction_master
      {
         PORT_WIRING 
         {
            PORT jtag_debug_trigout
            {
               width = "1";
               direction = "output";
               Is_Enabled = "0";
            }
            PORT jtag_debug_offchip_trace_clk
            {
               width = "1";
               direction = "output";
               Is_Enabled = "0";
            }
            PORT jtag_debug_offchip_trace_data
            {
               width = "18";
               direction = "output";
               Is_Enabled = "0";
            }
            PORT i_address
            {
               Is_Enabled = "1";
               direction = "output";
               type = "address";
               width = "26";
            }
            PORT i_read
            {
               Is_Enabled = "1";
               direction = "output";
               type = "read";
               width = "1";
            }
            PORT i_readdata
            {
               Is_Enabled = "1";
               direction = "input";
               type = "readdata";
               width = "32";
            }
            PORT i_waitrequest
            {
               Is_Enabled = "1";
               direction = "input";
               type = "waitrequest";
               width = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Instruction_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "0";
            Has_IRQ = "0";
            Irq_Scheme = "individual_requests";
            Interrupt_Range = "0-0";
            Is_Enabled = "1";
            Maximum_Burst_Size = "1";
            Burst_On_Burst_Boundaries_Only = "";
            Linewrap_Bursts = "";
            Interleave_Bursts = "";
         }
      }
      MASTER tightly_coupled_instruction_master_0
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Instruction_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_instruction_master_1
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Instruction_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "0";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_instruction_master_2
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Instruction_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "0";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_instruction_master_3
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Instruction_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "0";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER data_master
      {
         PORT_WIRING 
         {
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT d_address
            {
               Is_Enabled = "1";
               direction = "output";
               type = "address";
               width = "26";
            }
            PORT d_byteenable
            {
               Is_Enabled = "1";
               direction = "output";
               type = "byteenable";
               width = "4";
            }
            PORT d_irq
            {
               Is_Enabled = "1";
               direction = "input";
               type = "irq";
               width = "32";
            }
            PORT d_read
            {
               Is_Enabled = "1";
               direction = "output";
               type = "read";
               width = "1";
            }
            PORT d_readdata
            {