niosii_c.ptf

nios num clock verilog code

SYSTEM niosii_c
{
   System_Wizard_Version = "5.00";
   System_Wizard_Build = "171";
   WIZARD_SCRIPT_ARGUMENTS 
   {
      device_family = "CYCLONE";
      clock_freq = "50000000";
      generate_hdl = "1";
      generate_sdk = "0";
      do_build_sim = "1";
      hardcopy_compatible = "0";
      board_class = "";
      CLOCKS 
      {
         clk = "50000000";
      }
      hdl_language = "verilog";
      device_family_id = "CYCLONE";
      view_master_columns = "1";
      view_master_priorities = "0";
      name_column_width = "229";
      desc_column_width = "230";
      bustype_column_width = "0";
      base_column_width = "74";
      clock_column_width = "62";
      end_column_width = "73";
      view_frame_window = "maximized";
      BOARD_INFO 
      {
         altera_avalon_cfi_flash 
         {
            reference_designators = "";
         }
      }
      do_log_history = "0";
   }
   MODULE ext_flash
   {
      class = "altera_avalon_cfi_flash";
      class_version = "1.1";
      iss_model_name = "altera_avalon_flash";
      HDL_INFO 
      {
      }
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT data
            {
               width = "16";
               is_shared = "1";
               direction = "inout";
               type = "data";
            }
            PORT address
            {
               width = "20";
               is_shared = "1";
               direction = "input";
               type = "address";
            }
            PORT read_n
            {
               width = "1";
               is_shared = "1";
               direction = "input";
               type = "read_n";
            }
            PORT write_n
            {
               width = "1";
               is_shared = "0";
               direction = "input";
               type = "write_n";
            }
            PORT select_n
            {
               width = "1";
               is_shared = "0";
               direction = "input";
               type = "chipselect_n";
            }
         }
         WIZARD_SCRIPT_ARGUMENTS 
         {
            class = "altera_avalon_cfi_flash";
            Supports_Flash_File_System = "1";
            flash_reference_designator = "";
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon_tristate";
            Is_Nonvolatile_Storage = "1";
            Is_Memory_Device = "1";
            Address_Alignment = "dynamic";
            Has_IRQ = "0";
            Base_Address = "0x00200000";
            Data_Width = "16";
            Address_Width = "20";
            Simulation_Num_Lanes = "2";
            Convert_Xs_To_0 = "1";
            Write_Wait_States = "160ns";
            Read_Wait_States = "160ns";
            Setup_Time = "40ns";
            Hold_Time = "35ns";
            Address_Span = "2097152";
            MASTERED_BY ext_bus/tristate_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
            Is_Base_Locked = "1";
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Make_Memory_Model = "1";
         Is_Enabled = "1";
         Instantiate_In_System_Module = "0";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "clk";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Setup_Value = "40";
         Wait_Value = "160";
         Hold_Value = "35";
         Timing_Units = "ns";
         Unit_Multiplier = "1";
         Size = "2097152";
         MAKE 
         {
            MACRO 
            {
               EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX = "$(EXT_FLASH_FLASHTARGET_TMP1:0=)";
               EXT_FLASH_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";
               PAD_DAT_FILES = "--pad=0";
            }
            TARGET dat
            {
               ext_flash 
               {
                  Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
                  Command2 = "@echo Post-processing to create $(notdir $@)";
                  Command3 = "flash2dat --infile=$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash --outfile=$(SIMDIR)/ext_flash.dat --base=0x00200000 --end=0x3FFFFF $(PAD_DAT_FILES) --create-lanes=1 --width=16";
                  Dependency = "$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash";
                  Target_File = "$(SIMDIR)/ext_flash.dat";
               }
            }
            TARGET delete_placeholder_warning
            {
               ext_flash 
               {
                  Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
                  Is_Phony = "1";
                  Target_File = "do_delete_placeholder_warning";
               }
            }
            TARGET flashfiles
            {
               ext_flash 
               {
                  Command1 = "@echo Post-processing to create $(notdir $@)";
                  Command2 = "elf2flash --input=$(ELF) --flash= --boot=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir $(CPU_CLASS))/$(BOOT_COPIER) --outfile=$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --base=0x200000 --end=0x3FFFFF --reset=$(CPU_RESET_ADDRESS) ";
                  Dependency = "$(ELF)";
                  Target_File = "$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash";
               }
            }
            TARGET sym
            {
               ext_flash 
               {
                  Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
                  Command2 = "@echo Post-processing to create $(notdir $@)";
                  Command3 = "nios2-elf-nm -n $(ELF) > $(SIMDIR)/ext_flash.sym";
                  Dependency = "$(ELF)";
                  Target_File = "$(SIMDIR)/ext_flash.sym";
               }
            }
            MASTER cpu
            {
               MACRO 
               {
                  BOOT_COPIER = "boot_loader_cfi.srec";
                  CPU_CLASS = "altera_nios2";
                  CPU_RESET_ADDRESS = "0x200000";
               }
            }
         }
         contents_info = "SIMDIR/ext_flash_lane1.dat 1209871202 SIMDIR/ext_flash.dat 1209871202 SIMDIR/ext_flash_lane0.dat 1209871202 ";
      }
   }
   MODULE onchip_ram_4K
   {
      class = "altera_avalon_new_sdram_controller";
      class_version = "4.2";
      iss_model_name = "altera_memory";
      SLAVE s1
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Address_Alignment = "dynamic";
            Has_IRQ = "0";
            Maximum_Pending_Read_Transactions = "7";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            Is_Memory_Device = "1";
            Address_Width = "22";
            Data_Width = "32";
            Simulation_Num_Lanes = "1";
            MASTERED_BY cpu/instruction_master
            {
               priority = "1";
            }
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            Base_Address = "0x01000000";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
         }
         PORT_WIRING 
         {
            PORT zs_addr
            {
               direction = "output";
               width = "12";
               Is_Enabled = "1";
            }
            PORT zs_ba
            {
               direction = "output";
               width = "2";
               Is_Enabled = "1";
            }
            PORT zs_cas_n
            {
               direction = "output";
               width = "1";
               Is_Enabled = "1";
            }
            PORT zs_cke
            {
               direction = "output";
               width = "1";
               Is_Enabled = "1";
            }
            PORT zs_cs_n
            {
               direction = "output";
               width = "1";
               Is_Enabled = "1";
            }
            PORT zs_dq
            {
               direction = "inout";
               width = "32";
               Is_Enabled = "1";
            }
            PORT zs_dqm
            {
               direction = "output";
               width = "4";
               Is_Enabled = "1";
            }
            PORT zs_ras_n
            {
               direction = "output";
               width = "1";
               Is_Enabled = "1";
            }
            PORT zs_we_n
            {
               direction = "output";
               width = "1";
               Is_Enabled = "1";
            }
            PORT az_addr
            {
               Is_Enabled = "1";
               direction = "input";
               type = "address";
               width = "22";
            }
            PORT az_be_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "byteenable_n";
               width = "4";
            }
            PORT az_cs
            {
               Is_Enabled = "1";
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT az_data
            {
               Is_Enabled = "1";
               direction = "input";
               type = "writedata";
               width = "32";
            }
            PORT az_rd_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "read_n";
               width = "1";
            }
            PORT az_wr_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "write_n";
               width = "1";
            }
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT reset_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
            PORT za_data
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readdata";
               width = "32";
            }
            PORT za_valid
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readdatavalid";
               width = "1";
            }
            PORT za_waitrequest
            {
               Is_Enabled = "1";
               direction = "output";
               type = "waitrequest";
               width = "1";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Default_Module_Name = "sdram";
         Disable_Simulation_Port_Wiring = "0";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "clk";
         View 
         {
            Settings_Summary = "4194304 x 32<br>
                Memory size: 16 MBytes<br>
                128 MBits
                ";
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         register_data_in = "1";
         sim_model_base = "1";
         sdram_data_width = "32";
         sdram_addr_width = "12";
         sdram_row_width = "12";
         sdram_col_width = "8";
         sdram_num_chipselects = "1";
         sdram_num_banks = "4";
         refresh_period = "15.625";
         powerup_delay = "100";
         cas_latency = "3";
         t_rfc = "70";
         t_rp = "20";
         t_mrd = "3";
         t_rcd = "20";
         t_ac = "5.5";
         t_wr = "14";
         init_refresh_commands = "2";
         init_nop_delay = "0";
         shared_data = "0";
         starvation_indicator = "0";
         tristate_bridge_slave = "";
         is_initialized = "1";
         sdram_bank_width = "2";
         MAKE 
         {
            MACRO 
            {
               PAD_DAT_FILES = "--pad=0";
            }
            TARGET dat
            {
               onchip_ram_4K 
               {
                  Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
                  Command2 = "@echo Post-processing to create $(notdir $@)";
                  Command3 = "elf2dat --infile=$(ELF) --outfile=$(SIMDIR)/onchip_ram_4K.dat --base=0x01000000 --end=0x1FFFFFF $(PAD_DAT_FILES) --create-lanes=0 --width=32";
                  Dependency = "$(ELF)";
                  Target_File = "$(SIMDIR)/onchip_ram_4K.dat";
               }
            }
            TARGET delete_placeholder_warning
            {
               onchip_ram_4K 
               {
                  Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
                  Is_Phony = "1";
                  Target_File = "do_delete_placeholder_warning";
               }
            }
            TARGET sym
            {
               onchip_ram_4K 
               {
                  Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
                  Command2 = "@echo Post-processing to create $(notdir $@)";
                  Command3 = "nios2-elf-nm -n $(ELF) > $(SIMDIR)/onchip_ram_4K.sym";
                  Dependency = "$(ELF)";
                  Target_File = "$(SIMDIR)/onchip_ram_4K.sym";
               }
            }
         }
         contents_info = "SIMDIR/onchip_ram_4K.dat 1209871204 ";
      }
      SIMULATION 
      {