sha1_top_tb1.vhd

本算法基于leon2协处理器接口标准

----------------------------------------------------------------------------------------------
--
-- Fri Jan  4 15:12:08 2008
--
--      Design name        : sha1
--      Author             : nhm
--      Company            : asic
--
--      Description        : 
--
--
----------------------------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;


ENTITY sha1_top_tb IS

END sha1_top_tb;



ARCHITECTURE tb_behavioral OF sha1_top_tb IS

    --
    --half-cycle length
    --
    constant TPW  :  time := 10 ns ;
   
component sha1_top 
   PORT (
      TEXT_I0                 : IN std_logic_vector(63 DOWNTO 0);   -- Text input 64bit
      TEXT_I1                 : IN std_logic_vector(63 DOWNTO 0);   -- Text input 64bit
      TEXT_I2                 : IN std_logic_vector(63 DOWNTO 0);   -- Text input 64bit
      TEXT_I3                 : IN std_logic_vector(63 DOWNTO 0);   -- Text input 64bit

      --    Opcode_i is 9 bits
      --    000110000 means load hash high 256 bits
      --    000110001 means load hash low 256 bits
      --    000100010 means write back sha1 result high 128 bits
      --    000100011 means write back sha1 result low 32 bits        
      --    000100000 means operate sha1's first data block
      --    000100001 means operate sha1's other data blocks

      OPCODE_I                : IN std_logic_vector(8 DOWNTO 0);    -- command input
      START_I                 : IN std_logic;                       -- command input write enable
      LOAD_I                  : IN std_logic;                       -- command input the data

      CLK                     : IN std_logic;                       -- master clock input
      RST                     : IN std_logic;                       -- global reset input , active low  

      TEXT_O0                 : OUT std_logic_vector(63 DOWNTO 0);  -- Text output 64bit 
      TEXT_O1                 : OUT std_logic_vector(63 DOWNTO 0);  -- Text output 64bit (the former 32 bits are available)
      
      BUSY_O                  : OUT std_logic                       -- command Busy
          );
end component;

      SIGNAL        TEXT_I0_TB  :            std_logic_vector(63 DOWNTO 0);
      SIGNAL        TEXT_I1_TB  :            std_logic_vector(63 DOWNTO 0);
      SIGNAL        TEXT_I2_TB  :            std_logic_vector(63 DOWNTO 0);
      SIGNAL        TEXT_I3_TB  :            std_logic_vector(63 DOWNTO 0);

      SIGNAL        OPCODE_I_TB :            std_logic_vector(8 DOWNTO 0);
      SIGNAL        START_I_TB  :            std_logic;
      SIGNAL        LOAD_I_TB   :            std_logic;

      SIGNAL        CLK_TB      :            std_logic := '1';
      SIGNAL        RST_TB      :            std_logic;

      SIGNAL        TEXT_O0_TB  :            std_logic_vector(63 DOWNTO 0);
      SIGNAL        TEXT_O1_TB  :            std_logic_vector(63 DOWNTO 0);

      SIGNAL        BUSY_O_TB   :            std_logic;   
   
BEGIN

     -- Unit Under Test port map
 UUT: sha1_top
            port map(
                    TEXT_I0 => TEXT_I0_TB,
                    TEXT_I1 => TEXT_I1_TB,
                    TEXT_I2 => TEXT_I2_TB,
                    TEXT_I3 => TEXT_I3_TB,
                    
                    OPCODE_I => OPCODE_I_TB,
                    START_I  => START_I_TB,                    
                    LOAD_I   => LOAD_I_TB,
                    
                    CLK    => CLK_TB,
                    RST    => RST_TB,

                    TEXT_O0  => TEXT_O0_TB,
                    TEXT_O1  => TEXT_O1_TB,
                    
                    BUSY_O   => BUSY_O_TB
                    );

--CLK_tb <= '1';
clock_gen: process
	  begin
	    CLK_TB <= not CLK_TB;
		 wait for TPW;
	  end process;        --clock_gen


main: process
begin
 	

		-- Place stimulus here
     --wait for 5 ns;
     RST_TB <= '0';
     LOAD_I_TB <= '0'; 
     wait for 100 ns;
     
     RST_TB <= '1';
     START_I_TB <= '1';
     OPCODE_i_TB <= "000110001";

     wait for 20 ns;
     
     
     --START_I_TB <= '0';
     --OPCODE_i_TB <= "000000000";
     --wait for 20 ns;
     
     LOAD_I_TB <= '1';
     --START_I_TB <= '1';
     OPCODE_I_TB <= "000110000";
     TEXT_I3_TB <= X"0000000000000000";
     TEXT_I2_TB <= X"0000000000000000";
     TEXT_I1_TB <= X"0000000000000000";
     TEXT_I0_TB <= X"0000000061626380";
     wait for 20 ns;
     
     TEXT_I3_TB <= X"0000001800000000";
     TEXT_I2_TB <= X"0000000000000000";
     TEXT_I1_TB <= X"0000000000000000";
     TEXT_I0_TB <= X"0000000000000000";
     
     
     
     LOAD_I_TB <= '1';
     START_I_TB <= '0';
     OPCODE_i_TB <= "000000000";
     wait for 20 ns;
     
     LOAD_I_TB <= '0';          
     START_I_TB <= '0';
     --OPCODE_I_TB <= "000000000";
    
     
     wait for 1570 ns;
     
     START_I_TB <= '1';
     OPCODE_I_TB <= "000100010";
     wait for 20 ns;
     
     START_I_TB <= '1';
     OPCODE_I_TB <= "000100011";
     wait for 30 ns;
     
     START_I_TB <= '0';
     OPCODE_I_TB <= "000000000";
     wait for 20 ns;     
 
     
     START_I_TB <= '1';
     OPCODE_i_TB <= "000110001";

     wait for 20 ns;
     
     LOAD_I_TB <= '1';
     OPCODE_I_TB <= "000110000";
     TEXT_I3_TB <= X"0000000000000000";
     TEXT_I2_TB <= X"0000000000000000";
     TEXT_I1_TB <= X"0000000000000000";
     TEXT_I0_TB <= X"0000000061626380";
     wait for 20 ns;
     
     TEXT_I3_TB <= X"0000001800000000";
     TEXT_I2_TB <= X"0000000000000000";
     TEXT_I1_TB <= X"0000000000000000";
     TEXT_I0_TB <= X"0000000000000000";
     
     
     
     LOAD_I_TB <= '1';
     START_I_TB <= '0';
     OPCODE_i_TB <= "000000000";
     wait for 20 ns;
     
     LOAD_I_TB <= '0';          
     START_I_TB <= '0';
     
     wait for 1570 ns;
     
     START_I_TB <= '1';
     OPCODE_I_TB <= "000100010";
     wait for 20 ns;
     
     START_I_TB <= '1';
     OPCODE_I_TB <= "000100011";
     wait for 20 ns;
     wait;
end process;

 

END ARCHITECTURE tb_behavioral;