sha1_decoder.vhd

本算法基于leon2协处理器接口标准

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--
-- Fri Jan  4 15:12:08 2008
--
--      Design name        : sha1
--      Author             : nhm
--      Company            : asic
--
--      Description        : 
--
--
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY sha1_decoder IS
   PORT (
      OPCODE_I               : IN std_logic_vector(8 DOWNTO 0);
      START_I                : IN std_logic; 
        
      RST                    : IN std_logic;
      CLK                    : IN std_logic;   
 
      LSHH                   : OUT std_logic;
      LSHL                   : OUT std_logic;
      WSHAF                  : OUT std_logic;
      WSHAS                  : OUT std_logic;
      WS                     : OUT std_logic;
      SEL                    : OUT std_logic_vector(3 DOWNTO 0);
      ENABLE                 : OUT std_logic;
      COUNTER_O              : OUT std_logic_vector(6 DOWNTO 0);
      BUSY                   : OUT std_logic
         );
END sha1_decoder;

ARCHITECTURE behavioral OF sha1_decoder IS

   COMPONENT sha1_dff
     PORT( 		
           CLK      : in std_logic;
		     DATA_I   : in std_logic;
		     DATA_O   : out std_logic        

        );
   END COMPONENT;

   SIGNAL   COUNTER                :  std_logic_vector(6 DOWNTO 0);
   SIGNAL   LSHL_INTERNAL          :  std_logic;
   SIGNAL   LSHH_INTERNAL          :  std_logic;
   SIGNAL   LSHH1                  :  std_logic;
   SIGNAL   NOT0                   :  std_logic;
   SIGNAL   NOT79                  :  std_logic;
   SIGNAL   WSHAF_INTERNAL1        :  std_logic;
   SIGNAL   WSHAS_INTERNAL1        :  std_logic;   
   SIGNAL   WSHAF_INTERNAL2        :  std_logic;
   SIGNAL   WSHAS_INTERNAL2        :  std_logic;
   
BEGIN
   
   DFF0:  sha1_dff
   PORT MAP(      
      CLK   => CLK,
      
      DATA_I    => LSHL_INTERNAL,

      DATA_O    => LSHL
      );   
      
   DFF1:  sha1_dff
   PORT MAP(      
      CLK   => CLK,
      
      DATA_I    => LSHH_INTERNAL,

      DATA_O    => LSHH1
      );
      
   DFF2:  sha1_dff
   PORT MAP(      
      CLK   => CLK,
      
      DATA_I    => WSHAF_INTERNAL1,

      DATA_O    => WSHAF_INTERNAL2
      );
      
   DFF3:  sha1_dff
   PORT MAP(      
      CLK   => CLK,
      
      DATA_I    => WSHAS_INTERNAL1,

      DATA_O    => WSHAS_INTERNAL2
      );   
   DFF4:  sha1_dff
   PORT MAP(      
      CLK   => CLK,
      
      DATA_I    => WSHAF_INTERNAL2,

      DATA_O    => WSHAF
      );
      
   DFF5:  sha1_dff
   PORT MAP(      
      CLK   => CLK,
      
      DATA_I    => WSHAS_INTERNAL2,

      DATA_O    => WSHAS
      );  

   COUNTER_O <= COUNTER;
   LSHH <= LSHH1;
   
 PROCESS(CLK,OPCODE_I,COUNTER,START_I,LSHH1,NOT0,NOT79)
   BEGIN
     IF (CLK'event AND CLK = '1') THEN
      	  IF (RST = '0' OR COUNTER = "1001111") THEN              
        		    COUNTER <= "0000000";
          ELSE 
             IF(LSHH1 = '1') THEN    -- lshh
      		      COUNTER <= "0000001";
  	          END IF;
      		     
 		       IF (COUNTER /= "0000000") THEN     -- counter add 1
      		      COUNTER <= COUNTER +1; 
  	          END IF;
  	      END IF;
     END IF;
      
     -- to keep the control signals synchronize with the instructions
     LSHL_INTERNAL <= START_I AND (NOT OPCODE_I(8)) AND (NOT OPCODE_I(7)) AND (NOT OPCODE_I(6)) AND OPCODE_I(5) AND OPCODE_I(4) AND (NOT OPCODE_I(3)) AND (NOT OPCODE_I(2)) AND (NOT OPCODE_I(1)) AND OPCODE_I(0); 
        
     LSHH_INTERNAL <= START_I AND (NOT OPCODE_I(8)) AND (NOT OPCODE_I(7)) AND (NOT OPCODE_I(6)) AND OPCODE_I(5) AND OPCODE_I(4) AND (NOT OPCODE_I(3)) AND (NOT OPCODE_I(2)) AND (NOT OPCODE_I(1)) AND (NOT OPCODE_I(0)); 
        
     WSHAF_INTERNAL1 <= START_I AND (NOT OPCODE_I(8)) AND (NOT OPCODE_I(7)) AND (NOT OPCODE_I(6)) AND OPCODE_I(5) AND (NOT OPCODE_I(4)) AND (NOT OPCODE_I(3)) AND (NOT OPCODE_I(2)) AND OPCODE_I(1) AND (NOT OPCODE_I(0)); 
     WSHAS_INTERNAL1 <= START_I AND (NOT OPCODE_I(8)) AND (NOT OPCODE_I(7)) AND (NOT OPCODE_I(6)) AND OPCODE_I(5) AND (NOT OPCODE_I(4)) AND (NOT OPCODE_I(3)) AND (NOT OPCODE_I(2)) AND OPCODE_I(1) AND OPCODE_I(0); 
     
     IF (COUNTER /= "0000000") THEN
         NOT0 <= '1';
     ELSE
         NOT0 <= '0'; 
     END IF;
     
     IF (COUNTER /= "1001111") THEN
         NOT79 <= '1';
     ELSE
         NOT79 <= '0'; 
     END IF;
 
     BUSY <= LSHH1 OR (NOT0 AND NOT79);                    -- control busy signal
  
     
     IF (LSHH1 = '1' OR COUNTER /= "0000000") THEN         -- control enable signal
         ENABLE <= '1'; --BUSY <= '1';
     ELSE 
         ENABLE <= '0'; --BUSY <= '0'; 
     END IF;
     
     
     IF (COUNTER < "0000100") THEN                         -- control sel and ws signals
     	  SEL <= "0001"; WS <= '0';
     END IF;
     
     IF (COUNTER >= "0000100" AND COUNTER < "0001000") THEN
     	  SEL <= "0010";
     END IF;
     
     IF (COUNTER >= "0001000" AND COUNTER < "0001100") THEN
        SEL <= "0100";
     END IF;
     	
     IF (COUNTER >= "0001100" AND COUNTER < "0010000") THEN
     	  SEL <= "1000";
     END IF;
     
     IF (COUNTER = "0010000") THEN
     	  SEL <= "1111";
     	  WS <='1';
     END IF;
     
     IF (COUNTER > "0010000" AND COUNTER < "1010000") THEN
        SEL <= "1111";
     END IF;
     
         
 END PROCESS;    

   
END  behavioral;