sha1_top.vhd

本算法基于leon2协处理器接口标准

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--
-- Fri Jan  4 15:12:08 2008
--
--      Design name        : sha1
--      Author             : nhm
--      Company            : asic
--
--      Description        : 
--
--
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;


ENTITY sha1_top IS
   PORT (
      CLK                   : IN std_logic;                       -- master clock input
      RST                   : IN std_logic;                       -- global reset input , active low      
      TEXT_I0                 : IN std_logic_vector(63 DOWNTO 0);   -- Text input 64bit
      TEXT_I1                 : IN std_logic_vector(63 DOWNTO 0);   -- Text input 64bit
      TEXT_I2                 : IN std_logic_vector(63 DOWNTO 0);   -- Text input 64bit
      TEXT_I3                 : IN std_logic_vector(63 DOWNTO 0);   -- Text input 64bit

      --    Opcode_i is 9 bits
      --    000110000 means load hash high 256 bits
      --    000110001 means load hash low 256 bits
      --    000100010 means write back sha1 result high 128 bits
      --    000100011 means write back sha1 result low 32 bits 

      OPCODE_I                : IN std_logic_vector(8 DOWNTO 0);    -- command input
      START_I                 : IN std_logic;                       -- command input write enable
      LOAD_I                  : IN std_logic;
      TEXT_O0                 : OUT std_logic_vector(63 DOWNTO 0);  -- Text output 64bit 
      TEXT_O1                 : OUT std_logic_vector(63 DOWNTO 0);  -- Text output 64bit (the former 32 bits are available)
      BUSY_O                  : OUT std_logic                       -- command Busy
          );
END sha1_top;



ARCHITECTURE behavioral OF sha1_top IS

   COMPONENT sha1_decoder 
     PORT(
      OPCODE_I               : IN std_logic_vector(8 DOWNTO 0);
      START_I                : IN std_logic;   
      
      RST                    : IN std_logic;                       -- active low
      CLK                    : IN std_logic;                       -- master clock
 
      LSHH                   : OUT std_logic;
      LSHL                   : OUT std_logic;
      WSHAF                  : OUT std_logic;
      WSHAS                  : OUT std_logic;
      WS                     : OUT std_logic;
      SEL                    : OUT std_logic_vector(3 DOWNTO 0);
      ENABLE                 : OUT std_logic;
      COUNTER_O              : OUT std_logic_vector(6 DOWNTO 0);
      BUSY                   : OUT std_logic
         );
   END COMPONENT; 
   
   COMPONENT sha1_reg
     PORT(
        LOAD_I   :      IN      std_logic;
               
        DATA_I   :      IN      std_logic_vector(255 DOWNTO 0);     
        WT       :      IN      std_logic_vector(31 DOWNTO 0);
        
        LSHH     :      IN      std_logic;
        LSHL     :      IN      std_logic;
        WS       :      IN      std_logic;                         -- write serial
        SEL      :      IN      std_logic_vector(3 DOWNTO 0);
        
        CLK      :      IN      std_logic;                         -- master clock
        RST      :      IN      std_logic;                         -- active low
        
        DATA_O   :      OUT     std_logic_vector(127 DOWNTO 0)
        );
   END COMPONENT; 
   
   COMPONENT sha1_wt
     PORT (
      W13_I                 : IN std_logic_vector(31 DOWNTO 0);   
      W8_I                  : IN std_logic_vector(31 DOWNTO 0);   
      W2_I                  : IN std_logic_vector(31 DOWNTO 0);   
      W0_I                  : IN std_logic_vector(31 DOWNTO 0);
      
      COUNTER               : IN std_logic_vector(6  DOWNTO 0);
         
      CLK                   : IN std_logic;                        -- master clock

      WT_O                  : OUT std_logic_vector(31 DOWNTO 0)
          );
   END COMPONENT;
   
   COMPONENT sha1_counter
     PORT (
      WT                : IN std_logic_vector(31 DOWNTO 0); 
        
      LSHH              : IN std_logic;
      LSHL              : IN std_logic;
      WSHAF             : IN std_logic;
      WSHAS             : IN std_logic;                           
      COUNTER           : IN std_logic_vector(6 DOWNTO 0);
      ENABLE            : IN std_logic;
      
      CLK               : IN std_logic;                            -- master clock
      RST               : IN std_logic;                            -- active low
      
      TEXT0             : OUT std_logic_vector(63 DOWNTO 0);
      TEXT1             : OUT std_logic_vector(63 DOWNTO 0)
          );
   END COMPONENT; 

   
   SIGNAL LSHH_INTERNAL             :  std_logic;  
   SIGNAL LSHL_INTERNAL             :  std_logic;
   SIGNAL WSHAF_INTERNAL            :  std_logic; 
   SIGNAL WSHAS_INTERNAL            :  std_logic;
   SIGNAL WS_INTERNAL               :  std_logic; 
   SIGNAL SEL_INTERNAL              :  std_logic_vector(3 DOWNTO 0);
   SIGNAL ENABLE_INTERNAL           :  std_logic;                          
   SIGNAL COUNTER_O_INTERNAL        :  std_logic_vector(6 DOWNTO 0);
   SIGNAL WT_INTERNAL               :  std_logic_vector(31 DOWNTO 0);
   SIGNAL W13_INTERNAL              :  std_logic_vector(31 DOWNTO 0);
   SIGNAL W8_INTERNAL               :  std_logic_vector(31 DOWNTO 0);
   SIGNAL W2_INTERNAL               :  std_logic_vector(31 DOWNTO 0);
   SIGNAL W0_INTERNAL               :  std_logic_vector(31 DOWNTO 0);
   SIGNAL LOAD_INTERNAL             :  std_logic;   


BEGIN
   
DECODER:  sha1_decoder
   PORT MAP(
      OPCODE_I    => OPCODE_I, 
      START_I     => START_I,
      
      CLK  => CLK,
      RST  => RST,
      
      LSHH        => LSHH_INTERNAL,
      LSHL        => LSHL_INTERNAL,
      WSHAF       => WSHAF_INTERNAL,
      WSHAS       => WSHAS_INTERNAL,
      WS          => WS_INTERNAL,
      SEL         => SEL_INTERNAL,
      ENABLE      => ENABLE_INTERNAL,
      COUNTER_O   => COUNTER_O_INTERNAL,
      BUSY        => BUSY_O
      );
      
REG:  sha1_reg
   PORT MAP(
      DATA_I(63 DOWNTO 0)    => TEXT_I0,
      DATA_I(127 DOWNTO 64)  => TEXT_I1,
      DATA_I(191 DOWNTO 128) => TEXT_I2,
      DATA_I(255 DOWNTO 192) => TEXT_I3,
      
      WT => WT_INTERNAL,
      LOAD_I => LOAD_I,
      
      LSHH => LSHH_INTERNAL,
      LSHL => LSHL_INTERNAL,     
      WS   => WS_INTERNAL,
      SEL  => SEL_INTERNAL,
            
      CLK => CLK,
      RST => RST,   
   
      DATA_O(31 DOWNTO 0)   => W0_INTERNAL,
      DATA_O(63 DOWNTO 32)  => W2_INTERNAL,
      DATA_O(95 DOWNTO 64)  => W8_INTERNAL,
      DATA_O(127 DOWNTO 96) => W13_INTERNAL
      );
      
WT:  sha1_wt
   PORT MAP(
      W0_I  => W0_INTERNAL,
      W2_I  => W2_INTERNAL,
      W8_I  => W8_INTERNAL,
      W13_I => W13_INTERNAL,
      
      COUNTER => COUNTER_O_INTERNAL,
     
      CLK => CLK,
      
      WT_O => WT_INTERNAL
      );
      
COUNTER:  sha1_counter
   PORT MAP(
      WT => WT_INTERNAL,
   
      LSHH        => LSHH_INTERNAL,
      LSHL        => LSHL_INTERNAL,
      WSHAF       => WSHAF_INTERNAL,
      WSHAS       => WSHAS_INTERNAL,
      COUNTER     => COUNTER_O_INTERNAL,
      ENABLE      => ENABLE_INTERNAL,
      
      CLK => CLK,
      RST => RST,
      
      TEXT0 => TEXT_O0,
      TEXT1 => TEXT_O1
      );             
   
END behavioral;