sha1_counter.vhd

本算法基于leon2协处理器接口标准

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--
-- Fri Jan  4 15:12:08 2008
--
--      Design name        : sha1
--      Author             : nhm
--      Company            : asic
--
--      Description        : 
--
--
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY sha1_counter IS
   PORT (
      WT                : IN std_logic_vector(31 DOWNTO 0);
         
      LSHH              : IN std_logic;
      LSHL              : IN std_logic;
      WSHAF             : IN std_logic;
      WSHAS             : IN std_logic;                           
      COUNTER           : IN std_logic_vector(6 DOWNTO 0);
      ENABLE            : IN std_logic;
      
      CLK               : IN std_logic;
      RST               : IN std_logic;
      
      TEXT0             : OUT std_logic_vector(63 DOWNTO 0);
      TEXT1             : OUT std_logic_vector(63 DOWNTO 0)
          );
END sha1_counter;

ARCHITECTURE behavioral OF sha1_counter IS

  COMPONENT sha1_add_pack
  PORT (
              A          : IN  std_logic_vector(31 DOWNTO 0);
              Ft         : IN  std_logic_vector(31 DOWNTO 0);
              Wt        : IN  std_logic_vector(31 DOWNTO 0);
              Kt         : IN  std_logic_vector(31 DOWNTO 0);
              E          : IN  std_logic_vector(31 DOWNTO 0);
              H0        : IN  std_logic_vector(31 DOWNTO 0);
              SUM0    : OUT std_logic_vector(31 DOWNTO 0);
              SUM1    : OUT std_logic_vector(31 DOWNTO 0)
          );
  END COMPONENT;

  COMPONENT sha1_32add
  PORT (
          a      : in std_logic_vector(31 DOWNTO 0);
          b      : in std_logic_vector(31 DOWNTO 0);
          c      : out std_logic_vector(31 DOWNTO 0)
          );
  END COMPONENT;
        


   SIGNAL A                          :  std_logic_vector(31 DOWNTO 0);  
   SIGNAL B                          :  std_logic_vector(31 DOWNTO 0);  
   SIGNAL C                          :  std_logic_vector(31 DOWNTO 0);  
   SIGNAL D                          :  std_logic_vector(31 DOWNTO 0); 
   SIGNAL E                           :  std_logic_vector(31 DOWNTO 0); 
   SIGNAL H0                         :  std_logic_vector(31 DOWNTO 0); 
   SIGNAL H1                         :  std_logic_vector(31 DOWNTO 0);  
   SIGNAL H2                         :  std_logic_vector(31 DOWNTO 0);
   SIGNAL H3                         :  std_logic_vector(31 DOWNTO 0);  
   SIGNAL H4                         :  std_logic_vector(31 DOWNTO 0);
   SIGNAL SHA1_KT               :  std_logic_vector(31 DOWNTO 0); 
   SIGNAL SHA1_FT                :  std_logic_vector(31 DOWNTO 0); 
   SIGNAL NEXT_A                 :  std_logic_vector(31 DOWNTO 0); 
   SIGNAL NEXT_C                 :  std_logic_vector(31 DOWNTO 0);
   SIGNAL SHIFT_A                :  std_logic_vector(31 DOWNTO 0);
   SIGNAL H0_MUX                 :  std_logic_vector(31 DOWNTO 0);
   SIGNAL H1_INTERNAL         :  std_logic_vector(31 DOWNTO 0);
   SIGNAL H2_INTERNAL         :  std_logic_vector(31 DOWNTO 0);
   SIGNAL H3_INTERNAL         :  std_logic_vector(31 DOWNTO 0);
   SIGNAL H4_INTERNAL         :  std_logic_vector(31 DOWNTO 0);
   SIGNAL SUM0_INTERNAL     :  std_logic_vector(31 DOWNTO 0);
   SIGNAL SUM1_INTERNAL     :  std_logic_vector(31 DOWNTO 0);
   

BEGIN

   ADD_PACK: sha1_add_pack
   PORT MAP(
          A        => SHIFT_A,
          Ft       => SHA1_FT,
          Wt       => Wt,
          Kt       => SHA1_KT,
          E        => E, 
          H0      => H0_MUX,
          SUM0  => SUM0_INTERNAL,
          SUM1  => SUM1_INTERNAL	
      );

    ADD0:  sha1_32add
    PORT MAP(
          a   => SUM0_INTERNAL,
          b   => SUM1_INTERNAL,
          c   => NEXT_A
          );

    ADD1:  sha1_32add
    PORT MAP(
          a   => A,
          b   => H1,
          c   => H1_INTERNAL
          );     

    ADD2:  sha1_32add
    PORT MAP(
          a   => NEXT_C,
          b   => H2,
          c   => H2_INTERNAL
          ); 

    ADD3:  sha1_32add
    PORT MAP(
          a   => C,
          b   => H3,
          c   => H3_INTERNAL
          );

    ADD4:  sha1_32add
    PORT MAP(
          a   => D,
          b   => H4,
          c   => H4_INTERNAL
          );   
          
	--------------------------------------------------------------------	
	-- SHA COUNTER
	--------------------------------------------------------------------
   
Main_PROC:  PROCESS(CLK,LSHL,WSHAF,WSHAS,COUNTER,ENABLE)
   BEGIN
      
    IF (CLK'event AND CLK = '1') THEN
      IF (RST = '0') THEN                    -- reset '0' is active  
                 H0 <= X"67452301";    
                 H1 <= X"EFCDAB89";    
                 H2 <= X"98BADCFE";    
                 H3 <= X"10325476";    
                 H4 <= X"C3D2E1F0"; 
                 
                 A <= X"00000000";    
                 B <= X"00000000";    
                 C <= X"00000000";    
                 D <= X"00000000";    
                 E <= X"00000000";    

      ELSE   
        IF(ENABLE = '1') THEN               -- control the compute
                  E <= D;    
                  D <= C;    
                  C <= NEXT_C;    
                  B <= A;    
                  A <= NEXT_A;
        END IF;
        -- SELECT H0'S VALUE
      IF (COUNTER = "1001110") THEN
                  H0_MUX <= H0;
      ELSE
                  H0_MUX <= X"00000000";
      END IF;          
        
        IF (COUNTER = "1001111") THEN       -- the last counter
                  H0 <= NEXT_A;    
                  H1 <= H1_INTERNAL;    
                  H2 <= H2_INTERNAL;    
                  H3 <= H3_INTERNAL;    
                  H4 <= H4_INTERNAL;
        END IF;
      END IF;

      

      
      IF (LSHL = '1') THEN                  -- message's low 256 bits
            A <= H0;
            B <= H1;
            C <= H2;
            D <= H3;
            E <= H4;
      END IF;

      IF (WSHAF = '1') THEN                  --write back low 128 bits
            H0 <= X"67452301";    
            H1 <= X"EFCDAB89";    
            H2 <= X"98BADCFE";    
            H3 <= X"10325476"; 
      END IF;
 
      IF (WSHAS = '1') THEN                   --write back high 32 bits
            H4 <= X"C3D2E1F0"; 
      END IF;  
      
    END IF;

   
   end process;
   


 
   SHIFT_A <= A(26 DOWNTO 0) & A(31 DOWNTO 27);

   ---NEXT_A <= A(26 DOWNTO 0) & A(31 DOWNTO 27) + SHA1_FT + E + SHA1_KT + WT ;
   NEXT_C <= B(1 DOWNTO 0) & B(31 DOWNTO 2) ;


	--------------------------------------------------------------------	
	-- SHA1_ft and SHA1_KT generator
	--------------------------------------------------------------------   


ft_PROC:  PROCESS(B,C,D,COUNTER)             
   BEGIN      
         IF (COUNTER < "0010100") THEN
            SHA1_FT <= (B AND C) OR (NOT B AND D); 
            SHA1_KT <= X"5A827999";   
         ELSE
            IF (COUNTER < "0101000") THEN
               SHA1_FT <= B XOR C XOR D;
               SHA1_KT <= X"6ED9EBA1";    
            ELSE
               IF (COUNTER < "0111100") THEN
                  SHA1_FT <= ((B AND C) OR (C AND D)) OR (B AND D);
                  SHA1_KT <= X"8F1BBCDC";    
               ELSE
                  SHA1_FT <= (B XOR C) XOR D;
                  SHA1_KT <= X"CA62C1D6"; 
               END IF;
            END IF;
         END IF;
   END PROCESS;

	--------------------------------------------------------------------	
	-- the result generator
	-------------------------------------------------------------------- 

Read_PROC:  PROCESS(H0,H1,H2,H3,H4,WSHAF,WSHAS)
   BEGIN
			 --TEXT0(63 DOWNTO 32) <= H1;
			 --TEXT1 <= H3& H2;
			 
			 --IF (WSHAF = '1') THEN 
			 
			 --   TEXT0(31 DOWNTO 0) <= H0;
			 
			 --ELSE 
			 
			 --   TEXT0(31 DOWNTO 0) <= H4;
			 
			 --END IF;  
			 
			 TEXT0 <= H1&H0;
			 TEXT1 <= H3&H2;
			  
			 IF (WSHAS = '1') THEN
			    TEXT0(63 DOWNTO 32) <= X"00000000";
			 
			    TEXT0(31 DOWNTO 0) <= H4;
			 END IF; 
			 
			  
       
   END PROCESS;


END  behavioral;