booth16.v

来自「Booth Algorithm 是一種較簡潔的有號數字相乘的方法」· Verilog 代码 · 共 56 行

module Booth16(CLK, RESET, A, B, P);
parameter WIDTH = 16;
input  CLK, RESET;
input  [WIDTH-1:0]A, B;
output [WIDTH+WIDTH-1:0]P;
reg    [WIDTH+WIDTH-1:0]P;
reg    [WIDTH-1:0]Count;
reg    [WIDTH+WIDTH:0]PB;

always@(posedge CLK or negedge RESET)
begin
 if(!RESET)
   begin
     P = 0;
     Count = 0;
     PB = 0;
   end
 else
   begin
     PB[WIDTH+WIDTH:0] = {16'd0, B, 1'b0};
     for(Count = 0; Count < WIDTH; Count = Count + 1)
       begin
         casez(PB[1:0])
                2'b01:
                      begin
                        PB[WIDTH+WIDTH:WIDTH+1] = PB[WIDTH+WIDTH:WIDTH+1] + A[WIDTH-1:0];
                       begin
                        if(PB[WIDTH+WIDTH] == 0)
                            PB[WIDTH+WIDTH:0] = {1'b0, PB[WIDTH+WIDTH:1]};
                        else
                            PB[WIDTH+WIDTH:0] = {1'b1, PB[WIDTH+WIDTH:1]};
                       end
                      end
                2'b10:
                      begin
                        PB[WIDTH+WIDTH:WIDTH+1] = PB[WIDTH+WIDTH:WIDTH+1] - A[WIDTH-1:0];
                       begin
                        if(PB[WIDTH+WIDTH] == 0)
                           PB[WIDTH+WIDTH:0] = {1'b0, PB[WIDTH+WIDTH:1]};
                        else
                           PB[WIDTH+WIDTH:0] = {1'b1, PB[WIDTH+WIDTH:1]};
                       end
                      end 
              default:
                      begin
                        if(PB[WIDTH+WIDTH] == 0)
                           PB[WIDTH+WIDTH:0] = {1'b0, PB[WIDTH+WIDTH:1]};
                        else
                           PB[WIDTH+WIDTH:0] = {1'b1, PB[WIDTH+WIDTH:1]};
                       end
          endcase
        end
      end
 P[WIDTH+WIDTH-1:0] = PB[WIDTH+WIDTH:1];
end
endmodule