booth16_test.v

来自「Booth Algorithm 是一種較簡潔的有號數字相乘的方法」· Verilog 代码 · 共 74 行

module testbench();
parameter WIDTH = 16;

reg  CLK, RESET;
reg  [WIDTH-1:0]A, B;
wire [WIDTH+WIDTH-1:0]P;

Booth16  m1(.CLK(CLK), .RESET(RESET), .A(A), .B(B), .P(P));

initial
CLK = 1'b0;
always #50 CLK = !CLK;

initial
begin
RESET = 1'b0;
#10 RESET = 1'b1;
end

initial
begin
A = 16'd0;
B = 16'd0;
#50
A = 16'd10;
B = 16'd5;
#100
A = 16'd12;
B = 16'd24;
#100
A = 16'd100;
B = 16'd30;
#100
A = 16'd2;
B = 16'd1;
#100
A = 16'd200;
B = 16'd124;
#100
A = 16'd0;
B = 16'd14;
#100
A = 16'd17;
B = 16'd256;
#100
A = 16'd256;
B = 16'd256;
#100
A = 16'd12;
B = 16'd0;
#100
A = 16'd8;
B = 16'd4;
#100
A = 16'hFFFF;
B = 16'd10;
#100
A = 16'd32;
B = 16'hFAFA;
#100
A = 16'hFFFA;
B = 16'hFFFE;
#100
A = 16'd12;
B = 16'd24;
end

initial
begin
#10000 $finish;
end
endmodule