prev_cmp_freq_ram_ctrl.qmsg

使用VHDL语言描述AD0809芯片功能

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 18 15:58:34 2008 " "Info: Processing started: Sun May 18 15:58:34 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off freq_ram_ctrl -c freq_ram_ctrl " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off freq_ram_ctrl -c freq_ram_ctrl" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "freq_ram_ctrl.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file freq_ram_ctrl.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 freq_ram_ctrl-freq_ram_ctrl " "Info: Found design unit 1: freq_ram_ctrl-freq_ram_ctrl" {  } { { "freq_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/freq_ram_ctrl/freq_ram_ctrl.vhd" 20 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 freq_ram_ctrl " "Info: Found entity 1: freq_ram_ctrl" {  } { { "freq_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/freq_ram_ctrl/freq_ram_ctrl.vhd" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "freq_ram.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file freq_ram.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 freq_ram-SYN " "Info: Found design unit 1: freq_ram-SYN" {  } { { "freq_ram.vhd" "" { Text "D:/new AD/show_port/freq_ram_ctrl/freq_ram.vhd" 56 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 freq_ram " "Info: Found entity 1: freq_ram" {  } { { "freq_ram.vhd" "" { Text "D:/new AD/show_port/freq_ram_ctrl/freq_ram.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../show_port_pack.vhd 1 0 " "Info: Found 1 design units, including 0 entities, in source file ../show_port_pack.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 show_port_pack " "Info: Found design unit 1: show_port_pack" {  } { { "../show_port_pack.vhd" "" { Text "D:/new AD/show_port/show_port_pack.vhd" 4 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../divide10_99.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../divide10_99.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 divide10_99-SYN " "Info: Found design unit 1: divide10_99-SYN" {  } { { "../divide10_99.vhd" "" { Text "D:/new AD/show_port/divide10_99.vhd" 53 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 divide10_99 " "Info: Found entity 1: divide10_99" {  } { { "../divide10_99.vhd" "" { Text "D:/new AD/show_port/divide10_99.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../divide10_999.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../divide10_999.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 divide10_999-SYN " "Info: Found design unit 1: divide10_999-SYN" {  } { { "../divide10_999.vhd" "" { Text "D:/new AD/show_port/divide10_999.vhd" 53 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 divide10_999 " "Info: Found entity 1: divide10_999" {  } { { "../divide10_999.vhd" "" { Text "D:/new AD/show_port/divide10_999.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../divide10_9999.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../divide10_9999.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 divide10_9999-SYN " "Info: Found design unit 1: divide10_9999-SYN" {  } { { "../divide10_9999.vhd" "" { Text "D:/new AD/show_port/divide10_9999.vhd" 53 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 divide10_9999 " "Info: Found entity 1: divide10_9999" {  } { { "../divide10_9999.vhd" "" { Text "D:/new AD/show_port/divide10_9999.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "V_freq_pack.vhd 1 0 " "Info: Found 1 design units, including 0 entities, in source file V_freq_pack.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 V_freq_pack " "Info: Found design unit 1: V_freq_pack" {  } { { "V_freq_pack.vhd" "" { Text "D:/new AD/show_port/freq_ram_ctrl/V_freq_pack.vhd" 1 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "freq_ram_ctrl " "Info: Elaborating entity \"freq_ram_ctrl\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Error" "EVRFX_VHDL_EXPR_ELEMENT_NUMBER_MISMATCH" "7 8 freq_ram_ctrl.vhd(78) " "Error (10344): VHDL expression error at freq_ram_ctrl.vhd(78): expression has 7 elements, but must have 8 elements" {  } { { "freq_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/freq_ram_ctrl/freq_ram_ctrl.vhd" 78 0 0 } }  } 0 10344 "VHDL expression error at %3!s!: expression has %1!d! elements, but must have %2!d! elements" 0 0 "" 0}
{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Error: Can't elaborate top-level user hierarchy" {  } {  } 0 0 "Can't elaborate top-level user hierarchy" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "155 " "Info: Allocated 155 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Sun May 18 15:58:36 2008 " "Error: Processing ended: Sun May 18 15:58:36 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 2 s 0 s " "Error: Quartus II Full Compilation was unsuccessful. 2 errors, 0 warnings" {  } {  } 0 0 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}