freq_ram_ctrl.tan.qmsg

使用VHDL语言描述AD0809芯片功能

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "mem_read_clk memory memory freq_ram:freq_ram1\|altsyncram:altsyncram_component\|altsyncram_q5o1:auto_generated\|ram_block1a0~portb_address_reg0 freq_ram:freq_ram1\|altsyncram:altsyncram_component\|altsyncram_q5o1:auto_generated\|q_b\[0\] 163.03 MHz Internal " "Info: Clock \"mem_read_clk\" Internal fmax is restricted to 163.03 MHz between source memory \"freq_ram:freq_ram1\|altsyncram:altsyncram_component\|altsyncram_q5o1:auto_generated\|ram_block1a0~portb_address_reg0\" and destination memory \"freq_ram:freq_ram1\|altsyncram:altsyncram_component\|altsyncram_q5o1:auto_generated\|q_b\[0\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "3.067 ns 3.067 ns 6.134 ns " "Info: fmax restricted to Clock High delay (3.067 ns) plus Clock Low delay (3.067 ns) : restricted to 6.134 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.639 ns + Longest memory memory " "Info: + Longest memory to memory delay is 3.639 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns freq_ram:freq_ram1\|altsyncram:altsyncram_component\|altsyncram_q5o1:auto_generated\|ram_block1a0~portb_address_reg0 1 MEM M4K_X27_Y7 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X27_Y7; Fanout = 8; MEM Node = 'freq_ram:freq_ram1\|altsyncram:altsyncram_component\|altsyncram_q5o1:auto_generated\|ram_block1a0~portb_address_reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_q5o1.tdf" "" { Text "D:/new AD/show_port/freq_ram_ctrl/db/altsyncram_q5o1.tdf" 38 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.639 ns) 3.639 ns freq_ram:freq_ram1\|altsyncram:altsyncram_component\|altsyncram_q5o1:auto_generated\|q_b\[0\] 2 MEM M4K_X27_Y7 1 " "Info: 2: + IC(0.000 ns) + CELL(3.639 ns) = 3.639 ns; Loc. = M4K_X27_Y7; Fanout = 1; MEM Node = 'freq_ram:freq_ram1\|altsyncram:altsyncram_component\|altsyncram_q5o1:auto_generated\|q_b\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.639 ns" { freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|ram_block1a0~portb_address_reg0 freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|q_b[0] } "NODE_NAME" } } { "db/altsyncram_q5o1.tdf" "" { Text "D:/new AD/show_port/freq_ram_ctrl/db/altsyncram_q5o1.tdf" 34 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.639 ns ( 100.00 % ) " "Info: Total cell delay = 3.639 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.639 ns" { freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|ram_block1a0~portb_address_reg0 freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|q_b[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.639 ns" { freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|ram_block1a0~portb_address_reg0 {} freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|q_b[0] {} } { 0.000ns 0.000ns } { 0.000ns 3.639ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.057 ns - Smallest " "Info: - Smallest clock skew is -0.057 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mem_read_clk destination 2.921 ns + Shortest memory " "Info: + Shortest clock path from clock \"mem_read_clk\" to destination memory is 2.921 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns mem_read_clk 1 CLK PIN_24 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'mem_read_clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mem_read_clk } "NODE_NAME" } } { "freq_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/freq_ram_ctrl/freq_ram_ctrl.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.269 ns mem_read_clk~clkctrl 2 COMB CLKCTRL_G1 13 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G1; Fanout = 13; COMB Node = 'mem_read_clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { mem_read_clk mem_read_clk~clkctrl } "NODE_NAME" } } { "freq_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/freq_ram_ctrl/freq_ram_ctrl.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.831 ns) + CELL(0.821 ns) 2.921 ns freq_ram:freq_ram1\|altsyncram:altsyncram_component\|altsyncram_q5o1:auto_generated\|q_b\[0\] 3 MEM M4K_X27_Y7 1 " "Info: 3: + IC(0.831 ns) + CELL(0.821 ns) = 2.921 ns; Loc. = M4K_X27_Y7; Fanout = 1; MEM Node = 'freq_ram:freq_ram1\|altsyncram:altsyncram_component\|altsyncram_q5o1:auto_generated\|q_b\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.652 ns" { mem_read_clk~clkctrl freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|q_b[0] } "NODE_NAME" } } { "db/altsyncram_q5o1.tdf" "" { Text "D:/new AD/show_port/freq_ram_ctrl/db/altsyncram_q5o1.tdf" 34 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.951 ns ( 66.79 % ) " "Info: Total cell delay = 1.951 ns ( 66.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.970 ns ( 33.21 % ) " "Info: Total interconnect delay = 0.970 ns ( 33.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.921 ns" { mem_read_clk mem_read_clk~clkctrl freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|q_b[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.921 ns" { mem_read_clk {} mem_read_clk~combout {} mem_read_clk~clkctrl {} freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|q_b[0] {} } { 0.000ns 0.000ns 0.139ns 0.831ns } { 0.000ns 1.130ns 0.000ns 0.821ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mem_read_clk source 2.978 ns - Longest memory " "Info: - Longest clock path from clock \"mem_read_clk\" to source memory is 2.978 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns mem_read_clk 1 CLK PIN_24 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'mem_read_clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mem_read_clk } "NODE_NAME" } } { "freq_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/freq_ram_ctrl/freq_ram_ctrl.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.269 ns mem_read_clk~clkctrl 2 COMB CLKCTRL_G1 13 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G1; Fanout = 13; COMB Node = 'mem_read_clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { mem_read_clk mem_read_clk~clkctrl } "NODE_NAME" } } { "freq_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/freq_ram_ctrl/freq_ram_ctrl.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.831 ns) + CELL(0.878 ns) 2.978 ns freq_ram:freq_ram1\|altsyncram:altsyncram_component\|altsyncram_q5o1:auto_generated\|ram_block1a0~portb_address_reg0 3 MEM M4K_X27_Y7 8 " "Info: 3: + IC(0.831 ns) + CELL(0.878 ns) = 2.978 ns; Loc. = M4K_X27_Y7; Fanout = 8; MEM Node = 'freq_ram:freq_ram1\|altsyncram:altsyncram_component\|altsyncram_q5o1:auto_generated\|ram_block1a0~portb_address_reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.709 ns" { mem_read_clk~clkctrl freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_q5o1.tdf" "" { Text "D:/new AD/show_port/freq_ram_ctrl/db/altsyncram_q5o1.tdf" 38 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.008 ns ( 67.43 % ) " "Info: Total cell delay = 2.008 ns ( 67.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.970 ns ( 32.57 % ) " "Info: Total interconnect delay = 0.970 ns ( 32.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.978 ns" { mem_read_clk mem_read_clk~clkctrl freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.978 ns" { mem_read_clk {} mem_read_clk~combout {} mem_read_clk~clkctrl {} freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|ram_block1a0~portb_address_reg0 {} } { 0.000ns 0.000ns 0.139ns 0.831ns } { 0.000ns 1.130ns 0.000ns 0.878ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.921 ns" { mem_read_clk mem_read_clk~clkctrl freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|q_b[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.921 ns" { mem_read_clk {} mem_read_clk~combout {} mem_read_clk~clkctrl {} freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|q_b[0] {} } { 0.000ns 0.000ns 0.139ns 0.831ns } { 0.000ns 1.130ns 0.000ns 0.821ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.978 ns" { mem_read_clk mem_read_clk~clkctrl freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.978 ns" { mem_read_clk {} mem_read_clk~combout {} mem_read_clk~clkctrl {} freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|ram_block1a0~portb_address_reg0 {} } { 0.000ns 0.000ns 0.139ns 0.831ns } { 0.000ns 1.130ns 0.000ns 0.878ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" {  } { { "db/altsyncram_q5o1.tdf" "" { Text "D:/new AD/show_port/freq_ram_ctrl/db/altsyncram_q5o1.tdf" 38 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns + " "Info: + Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_q5o1.tdf" "" { Text "D:/new AD/show_port/freq_ram_ctrl/db/altsyncram_q5o1.tdf" 34 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.639 ns" { freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|ram_block1a0~portb_address_reg0 freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|q_b[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.639 ns" { freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|ram_block1a0~portb_address_reg0 {} freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|q_b[0] {} } { 0.000ns 0.000ns } { 0.000ns 3.639ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.921 ns" { mem_read_clk mem_read_clk~clkctrl freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|q_b[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.921 ns" { mem_read_clk {} mem_read_clk~combout {} mem_read_clk~clkctrl {} freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|q_b[0] {} } { 0.000ns 0.000ns 0.139ns 0.831ns } { 0.000ns 1.130ns 0.000ns 0.821ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.978 ns" { mem_read_clk mem_read_clk~clkctrl freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.978 ns" { mem_read_clk {} mem_read_clk~combout {} mem_read_clk~clkctrl {} freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|ram_block1a0~portb_address_reg0 {} } { 0.000ns 0.000ns 0.139ns 0.831ns } { 0.000ns 1.130ns 0.000ns 0.878ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|q_b[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|q_b[0] {} } { 0.000ns } { 0.109ns } "" } } { "db/altsyncram_q5o1.tdf" "" { Text "D:/new AD/show_port/freq_ram_ctrl/db/altsyncram_q5o1.tdf" 34 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk_32k register memory mem_write_addr\[2\] freq_ram:freq_ram1\|altsyncram:altsyncram_component\|altsyncram_q5o1:auto_generated\|ram_block1a0~porta_datain_reg3 163.03 MHz Internal " "Info: Clock \"clk_32k\" Internal fmax is restricted to 163.03 MHz between source register \"mem_write_addr\[2\]\" and destination memory \"freq_ram:freq_ram1\|altsyncram:altsyncram_component\|altsyncram_q5o1:auto_generated\|ram_block1a0~porta_datain_reg3\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "3.067 ns 3.067 ns 6.134 ns " "Info: fmax restricted to Clock High delay (3.067 ns) plus Clock Low delay (3.067 ns) : restricted to 6.134 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.848 ns + Longest register memory " "Info: + Longest register to memory delay is 4.848 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mem_write_addr\[2\] 1 REG LCFF_X28_Y7_N27 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X28_Y7_N27; Fanout = 12; REG Node = 'mem_write_addr\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mem_write_addr[2] } "NODE_NAME" } } { "freq_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/freq_ram_ctrl/freq_ram_ctrl.vhd" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.765 ns) + CELL(0.624 ns) 1.389 ns Mux4~387 2 COMB LCCOMB_X29_Y7_N0 2 " "Info: 2: + IC(0.765 ns) + CELL(0.624 ns) = 1.389 ns; Loc. = LCCOMB_X29_Y7_N0; Fanout = 2; COMB Node = 'Mux4~387'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.389 ns" { mem_write_addr[2] Mux4~387 } "NODE_NAME" } } { "freq_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/freq_ram_ctrl/freq_ram_ctrl.vhd" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.697 ns) + CELL(0.366 ns) 2.452 ns Mux3~351 3 COMB LCCOMB_X28_Y7_N20 1 " "Info: 3: + IC(0.697 ns) + CELL(0.366 ns) = 2.452 ns; Loc. = LCCOMB_X28_Y7_N20; Fanout = 1; COMB Node = 'Mux3~351'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.063 ns" { Mux4~387 Mux3~351 } "NODE_NAME" } } { "freq_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/freq_ram_ctrl/freq_ram_ctrl.vhd" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.417 ns) + CELL(0.650 ns) 3.519 ns Mux3~355 4 COMB LCCOMB_X28_Y7_N18 1 " "Info: 4: + IC(0.417 ns) + CELL(0.650 ns) = 3.519 ns; Loc. = LCCOMB_X28_Y7_N18; Fanout = 1; COMB Node = 'Mux3~355'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.067 ns" { Mux3~351 Mux3~355 } "NODE_NAME" } } { "freq_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/freq_ram_ctrl/freq_ram_ctrl.vhd" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.201 ns) + CELL(0.128 ns) 4.848 ns freq_ram:freq_ram1\|altsyncram:altsyncram_component\|altsyncram_q5o1:auto_generated\|ram_block1a0~porta_datain_reg3 5 MEM M4K_X27_Y7 1 " "Info: 5: + IC(1.201 ns) + CELL(0.128 ns) = 4.848 ns; Loc. = M4K_X27_Y7; Fanout = 1; MEM Node = 'freq_ram:freq_ram1\|altsyncram:altsyncram_component\|altsyncram_q5o1:auto_generated\|ram_block1a0~porta_datain_reg3'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.329 ns" { Mux3~355 freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|ram_block1a0~porta_datain_reg3 } "NODE_NAME" } } { "db/altsyncram_q5o1.tdf" "" { Text "D:/new AD/show_port/freq_ram_ctrl/db/altsyncram_q5o1.tdf" 38 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.768 ns ( 36.47 % ) " "Info: Total cell delay = 1.768 ns ( 36.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.080 ns ( 63.53 % ) " "Info: Total interconnect delay = 3.080 ns ( 63.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.848 ns" { mem_write_addr[2] Mux4~387 Mux3~351 Mux3~355 freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|ram_block1a0~porta_datain_reg3 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.848 ns" { mem_write_addr[2] {} Mux4~387 {} Mux3~351 {} Mux3~355 {} freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|ram_block1a0~porta_datain_reg3 {} } { 0.000ns 0.765ns 0.697ns 0.417ns 1.201ns } { 0.000ns 0.624ns 0.366ns 0.650ns 0.128ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.092 ns - Smallest " "Info: - Smallest clock skew is 0.092 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_32k destination 2.944 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk_32k\" to destination memory is 2.944 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk_32k 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk_32k'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_32k } "NODE_NAME" } } { "freq_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/freq_ram_ctrl/freq_ram_ctrl.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk_32k~clkctrl 2 COMB CLKCTRL_G2 27 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 27; COMB Node = 'clk_32k~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk_32k clk_32k~clkctrl } "NODE_NAME" } } { "freq_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/freq_ram_ctrl/freq_ram_ctrl.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.831 ns) + CELL(0.834 ns) 2.944 ns freq_ram:freq_ram1\|altsyncram:altsyncram_component\|altsyncram_q5o1:auto_generated\|ram_block1a0~porta_datain_reg3 3 MEM M4K_X27_Y7 1 " "Info: 3: + IC(0.831 ns) + CELL(0.834 ns) = 2.944 ns; Loc. = M4K_X27_Y7; Fanout = 1; MEM Node = 'freq_ram:freq_ram1\|altsyncram:altsyncram_component\|altsyncram_q5o1:auto_generated\|ram_block1a0~porta_datain_reg3'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.665 ns" { clk_32k~clkctrl freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|ram_block1a0~porta_datain_reg3 } "NODE_NAME" } } { "db/altsyncram_q5o1.tdf" "" { Text "D:/new AD/show_port/freq_ram_ctrl/db/altsyncram_q5o1.tdf" 38 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.974 ns ( 67.05 % ) " "Info: Total cell delay = 1.974 ns ( 67.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.970 ns ( 32.95 % ) " "Info: Total interconnect delay = 0.970 ns ( 32.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.944 ns" { clk_32k clk_32k~clkctrl freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|ram_block1a0~porta_datain_reg3 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.944 ns" { clk_32k {} clk_32k~combout {} clk_32k~clkctrl {} freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|ram_block1a0~porta_datain_reg3 {} } { 0.000ns 0.000ns 0.139ns 0.831ns } { 0.000ns 1.140ns 0.000ns 0.834ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_32k source 2.852 ns - Longest register " "Info: - Longest clock path from clock \"clk_32k\" to source register is 2.852 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk_32k 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk_32k'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_32k } "NODE_NAME" } } { "freq_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/freq_ram_ctrl/freq_ram_ctrl.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk_32k~clkctrl 2 COMB CLKCTRL_G2 27 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 27; COMB Node = 'clk_32k~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk_32k clk_32k~clkctrl } "NODE_NAME" } } { "freq_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/freq_ram_ctrl/freq_ram_ctrl.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.907 ns) + CELL(0.666 ns) 2.852 ns mem_write_addr\[2\] 3 REG LCFF_X28_Y7_N27 12 " "Info: 3: + IC(0.907 ns) + CELL(0.666 ns) = 2.852 ns; Loc. = LCFF_X28_Y7_N27; Fanout = 12; REG Node = 'mem_write_addr\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { clk_32k~clkctrl mem_write_addr[2] } "NODE_NAME" } } { "freq_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/freq_ram_ctrl/freq_ram_ctrl.vhd" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.32 % ) " "Info: Total cell delay = 1.806 ns ( 63.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.046 ns ( 36.68 % ) " "Info: Total interconnect delay = 1.046 ns ( 36.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.852 ns" { clk_32k clk_32k~clkctrl mem_write_addr[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.852 ns" { clk_32k {} clk_32k~combout {} clk_32k~clkctrl {} mem_write_addr[2] {} } { 0.000ns 0.000ns 0.139ns 0.907ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.944 ns" { clk_32k clk_32k~clkctrl freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|ram_block1a0~porta_datain_reg3 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.944 ns" { clk_32k {} clk_32k~combout {} clk_32k~clkctrl {} freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|ram_block1a0~porta_datain_reg3 {} } { 0.000ns 0.000ns 0.139ns 0.831ns } { 0.000ns 1.140ns 0.000ns 0.834ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.852 ns" { clk_32k clk_32k~clkctrl mem_write_addr[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.852 ns" { clk_32k {} clk_32k~combout {} clk_32k~clkctrl {} mem_write_addr[2] {} } { 0.000ns 0.000ns 0.139ns 0.907ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "freq_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/freq_ram_ctrl/freq_ram_ctrl.vhd" 69 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns + " "Info: + Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_q5o1.tdf" "" { Text "D:/new AD/show_port/freq_ram_ctrl/db/altsyncram_q5o1.tdf" 38 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.848 ns" { mem_write_addr[2] Mux4~387 Mux3~351 Mux3~355 freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|ram_block1a0~porta_datain_reg3 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.848 ns" { mem_write_addr[2] {} Mux4~387 {} Mux3~351 {} Mux3~355 {} freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|ram_block1a0~porta_datain_reg3 {} } { 0.000ns 0.765ns 0.697ns 0.417ns 1.201ns } { 0.000ns 0.624ns 0.366ns 0.650ns 0.128ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.944 ns" { clk_32k clk_32k~clkctrl freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|ram_block1a0~porta_datain_reg3 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.944 ns" { clk_32k {} clk_32k~combout {} clk_32k~clkctrl {} freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|ram_block1a0~porta_datain_reg3 {} } { 0.000ns 0.000ns 0.139ns 0.831ns } { 0.000ns 1.140ns 0.000ns 0.834ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.852 ns" { clk_32k clk_32k~clkctrl mem_write_addr[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.852 ns" { clk_32k {} clk_32k~combout {} clk_32k~clkctrl {} mem_write_addr[2] {} } { 0.000ns 0.000ns 0.139ns 0.907ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|ram_block1a0~porta_datain_reg3 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { freq_ram:freq_ram1|altsyncram:altsyncram_component|altsyncram_q5o1:auto_generated|ram_block1a0~porta_datain_reg3 {} } {  } {  } "" } } { "db/altsyncram_q5o1.tdf" "" { Text "D:/new AD/show_port/freq_ram_ctrl/db/altsyncram_q5o1.tdf" 38 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}