alt_u_div_k5f.tdf

使用VHDL语言描述AD0809芯片功能

--alt_u_div DEVICE_FAMILY="Cyclone II" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 SKIP_BITS=0 WIDTH_D=14 WIDTH_N=14 WIDTH_Q=14 WIDTH_R=14 denominator numerator quotient remainder
--VERSION_BEGIN 7.2 cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_abs 2006:04:25:14:52:42:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_divide 2007:01:30:03:58:02:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:05:02:16:27:14:SJ cbx_stratixii 2007:06:28:17:26:26:SJ cbx_util_mgl 2007:06:01:06:37:30:SJ  VERSION_END


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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
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--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
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--  without limitation, that your use is for the sole purpose of 
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FUNCTION add_sub_lkc (dataa[0..0], datab[0..0])
RETURNS ( cout, result[0..0]);
FUNCTION add_sub_mkc (dataa[1..0], datab[1..0])
RETURNS ( cout, result[1..0]);

--synthesis_resources = lut 114 
SUBDESIGN alt_u_div_k5f
( 
	den_out[13..0]	:	output;
	denominator[13..0]	:	input;
	numerator[13..0]	:	input;
	quotient[13..0]	:	output;
	remainder[13..0]	:	output;
) 
VARIABLE 
	add_sub_0 : add_sub_lkc;
	add_sub_1 : add_sub_mkc;
	add_sub_10_result_int[11..0]	:	WIRE;
	add_sub_10_cout	:	WIRE;
	add_sub_10_dataa[10..0]	:	WIRE;
	add_sub_10_datab[10..0]	:	WIRE;
	add_sub_10_result[10..0]	:	WIRE;
	add_sub_11_result_int[12..0]	:	WIRE;
	add_sub_11_cout	:	WIRE;
	add_sub_11_dataa[11..0]	:	WIRE;
	add_sub_11_datab[11..0]	:	WIRE;
	add_sub_11_result[11..0]	:	WIRE;
	add_sub_12_result_int[13..0]	:	WIRE;
	add_sub_12_cout	:	WIRE;
	add_sub_12_dataa[12..0]	:	WIRE;
	add_sub_12_datab[12..0]	:	WIRE;
	add_sub_12_result[12..0]	:	WIRE;
	add_sub_13_result_int[14..0]	:	WIRE;
	add_sub_13_cout	:	WIRE;
	add_sub_13_dataa[13..0]	:	WIRE;
	add_sub_13_datab[13..0]	:	WIRE;
	add_sub_13_result[13..0]	:	WIRE;
	add_sub_2_result_int[3..0]	:	WIRE;
	add_sub_2_cout	:	WIRE;
	add_sub_2_dataa[2..0]	:	WIRE;
	add_sub_2_datab[2..0]	:	WIRE;
	add_sub_2_result[2..0]	:	WIRE;
	add_sub_3_result_int[4..0]	:	WIRE;
	add_sub_3_cout	:	WIRE;
	add_sub_3_dataa[3..0]	:	WIRE;
	add_sub_3_datab[3..0]	:	WIRE;