alt_u_div_45f.tdf

使用VHDL语言描述AD0809芯片功能

--alt_u_div DEVICE_FAMILY="Cyclone II" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 SKIP_BITS=0 WIDTH_D=10 WIDTH_N=10 WIDTH_Q=10 WIDTH_R=10 denominator numerator quotient remainder
--VERSION_BEGIN 7.2 cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_abs 2006:04:25:14:52:42:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_divide 2007:01:30:03:58:02:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:05:02:16:27:14:SJ cbx_stratixii 2007:06:28:17:26:26:SJ cbx_util_mgl 2007:06:01:06:37:30:SJ  VERSION_END


-- Copyright (C) 1991-2007 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION add_sub_lkc (dataa[0..0], datab[0..0])
RETURNS ( cout, result[0..0]);
FUNCTION add_sub_mkc (dataa[1..0], datab[1..0])
RETURNS ( cout, result[1..0]);

--synthesis_resources = lut 60 
SUBDESIGN alt_u_div_45f
( 
	den_out[9..0]	:	output;
	denominator[9..0]	:	input;
	numerator[9..0]	:	input;
	quotient[9..0]	:	output;
	remainder[9..0]	:	output;
) 
VARIABLE 
	add_sub_0 : add_sub_lkc;
	add_sub_1 : add_sub_mkc;
	add_sub_2_result_int[3..0]	:	WIRE;
	add_sub_2_cout	:	WIRE;
	add_sub_2_dataa[2..0]	:	WIRE;
	add_sub_2_datab[2..0]	:	WIRE;
	add_sub_2_result[2..0]	:	WIRE;
	add_sub_3_result_int[4..0]	:	WIRE;
	add_sub_3_cout	:	WIRE;
	add_sub_3_dataa[3..0]	:	WIRE;
	add_sub_3_datab[3..0]	:	WIRE;
	add_sub_3_result[3..0]	:	WIRE;
	add_sub_4_result_int[5..0]	:	WIRE;
	add_sub_4_cout	:	WIRE;
	add_sub_4_dataa[4..0]	:	WIRE;
	add_sub_4_datab[4..0]	:	WIRE;
	add_sub_4_result[4..0]	:	WIRE;
	add_sub_5_result_int[6..0]	:	WIRE;
	add_sub_5_cout	:	WIRE;
	add_sub_5_dataa[5..0]	:	WIRE;
	add_sub_5_datab[5..0]	:	WIRE;
	add_sub_5_result[5..0]	:	WIRE;
	add_sub_6_result_int[7..0]	:	WIRE;
	add_sub_6_cout	:	WIRE;
	add_sub_6_dataa[6..0]	:	WIRE;
	add_sub_6_datab[6..0]	:	WIRE;
	add_sub_6_result[6..0]	:	WIRE;
	add_sub_7_result_int[8..0]	:	WIRE;
	add_sub_7_cout	:	WIRE;
	add_sub_7_dataa[7..0]	:	WIRE;
	add_sub_7_datab[7..0]	:	WIRE;
	add_sub_7_result[7..0]	:	WIRE;
	add_sub_8_result_int[9..0]	:	WIRE;
	add_sub_8_cout	:	WIRE;
	add_sub_8_dataa[8..0]	:	WIRE;
	add_sub_8_datab[8..0]	:	WIRE;
	add_sub_8_result[8..0]	:	WIRE;
	add_sub_9_result_int[10..0]	:	WIRE;
	add_sub_9_cout	:	WIRE;
	add_sub_9_dataa[9..0]	:	WIRE;
	add_sub_9_datab[9..0]	:	WIRE;
	add_sub_9_result[9..0]	:	WIRE;
	DenominatorIn[120..0]	: WIRE;