adc_0820.vho

使用VHDL语言描述AD0809芯片功能

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 7.2 Build 151 09/26/2007 SJ Full Version"

-- DATE "05/20/2008 11:25:07"

-- 
-- Device: Altera EP2C8Q208C8 Package PQFP208
-- 

-- 
-- This VHDL file should be used for PRIMETIME only
-- 

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY 	ADC_0820 IS
    PORT (
	cs_bar : OUT std_logic;
	rd_bar : OUT std_logic;
	int_bar : IN std_logic;
	wr_rdy : INOUT std_logic;
	clk_period : IN std_logic;
	clk_state : IN std_logic;
	lock : OUT std_logic
	);
END ADC_0820;

ARCHITECTURE structure OF ADC_0820 IS
SIGNAL GNDs : std_logic_vector(2048 DOWNTO 0);
SIGNAL VCCs : std_logic_vector(2048 DOWNTO 0);
SIGNAL gnd : std_logic;
SIGNAL vcc : std_logic;
SIGNAL ww_cs_bar : std_logic;
SIGNAL ww_rd_bar : std_logic;
SIGNAL ww_int_bar : std_logic;
SIGNAL ww_clk_period : std_logic;
SIGNAL ww_clk_state : std_logic;
SIGNAL ww_lock : std_logic;
SIGNAL \reset~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \clk_state~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \int_bar~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \clk_state~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \clk_state~clkctrl_modesel\ : std_logic;
SIGNAL \now_state.st0~feeder_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \now_state.st0~feeder_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \clk_period~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \q0~feeder_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \q0~feeder_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL reset_modesel : std_logic_vector(3 DOWNTO 0);
SIGNAL reset_pathsel : std_logic_vector(7 DOWNTO 0);
SIGNAL \reset~clkctrl_modesel\ : std_logic;
SIGNAL \now_state.st1~6_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \now_state.st1~6_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \wr_bar~feeder_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \wr_bar~feeder_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \now_state.st3~feeder_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \now_state.st3~feeder_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \now_state.st4~feeder_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \now_state.st4~feeder_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \now_state.st5~feeder_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \now_state.st5~feeder_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \Selector0~8_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \Selector0~8_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \now_state~34_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \now_state~34_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \rd_bar~0_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \rd_bar~0_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \lock~32_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \lock~32_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \wr_rdy~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \cs_bar~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \rd_bar~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \lock~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \int_bar~combout\ : std_logic;
SIGNAL \clk_state~combout\ : std_logic;
SIGNAL \clk_state~clkctrl_outclk\ : std_logic;
SIGNAL \now_state.st0~feeder_combout\ : std_logic;
SIGNAL \clk_period~combout\ : std_logic;
SIGNAL \q0~feeder_combout\ : std_logic;
SIGNAL \q0~regout\ : std_logic;
SIGNAL \q1~regout\ : std_logic;
SIGNAL \reset~combout\ : std_logic;
SIGNAL \reset~clkctrl_outclk\ : std_logic;
SIGNAL \now_state.st0~regout\ : std_logic;
SIGNAL \now_state.st1~6_combout\ : std_logic;
SIGNAL \now_state.st1~regout\ : std_logic;
SIGNAL \wr_bar~feeder_combout\ : std_logic;
SIGNAL \wr_bar~regout\ : std_logic;
SIGNAL \now_state.st3~feeder_combout\ : std_logic;
SIGNAL \now_state.st3~regout\ : std_logic;
SIGNAL \now_state.st4~feeder_combout\ : std_logic;
SIGNAL \now_state.st4~regout\ : std_logic;
SIGNAL \now_state.st5~feeder_combout\ : std_logic;
SIGNAL \now_state.st5~regout\ : std_logic;
SIGNAL \Selector0~8_combout\ : std_logic;
SIGNAL \now_state.st6~regout\ : std_logic;
SIGNAL \now_state~34_combout\ : std_logic;
SIGNAL \now_state.st7~regout\ : std_logic;
SIGNAL \rd_bar~0_combout\ : std_logic;
SIGNAL \rd_bar~reg0_regout\ : std_logic;
SIGNAL \lock~32_combout\ : std_logic;
SIGNAL \lock~reg0_regout\ : std_logic;
SIGNAL \ALT_INV_rd_bar~reg0_regout\ : std_logic;
SIGNAL \ALT_INV_wr_bar~regout\ : std_logic;
COMPONENT cycloneii_lcell_comb
PORT (
	dataa : IN STD_LOGIC;
	datab : IN STD_LOGIC;
	datac : IN STD_LOGIC;
	datad : IN STD_LOGIC;
	cin : IN STD_LOGIC;
	combout : OUT STD_LOGIC;
	cout : OUT STD_LOGIC;
	modesel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	pathsel : IN STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;

COMPONENT cycloneii_lcell_ff
PORT (
	clk : IN STD_LOGIC;
	datain : IN STD_LOGIC;
	sdata : IN STD_LOGIC;
	aclr : IN STD_LOGIC;
	sclr : IN STD_LOGIC;
	sload : IN STD_LOGIC;
	ena : IN STD_LOGIC;
	regout : OUT STD_LOGIC);
END COMPONENT;

COMPONENT cycloneii_io
PORT (
	datain : IN STD_LOGIC;
	oe : IN STD_LOGIC;
	outclk : IN STD_LOGIC;
	outclkena : IN STD_LOGIC;
	inclk : IN STD_LOGIC;
	inclkena : IN STD_LOGIC;
	areset : IN STD_LOGIC;
	sreset : IN STD_LOGIC;
	differentialin : IN STD_LOGIC;
	linkin : IN STD_LOGIC;
	combout : OUT STD_LOGIC;
	regout : OUT STD_LOGIC;
	differentialout : OUT STD_LOGIC;
	linkout : OUT STD_LOGIC;
	padio : INOUT STD_LOGIC;
	modesel : IN STD_LOGIC_VECTOR(25 DOWNTO 0));
END COMPONENT;

COMPONENT cycloneii_clkctrl
PORT (
	ena : IN STD_LOGIC;
	inclk : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	clkselect : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
	outclk : OUT STD_LOGIC;
	modesel : IN STD_LOGIC);
END COMPONENT;


COMPONENT INV
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;

COMPONENT AND1
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;
BEGIN

cs_bar <= ww_cs_bar;
rd_bar <= ww_rd_bar;
ww_int_bar <= int_bar;
ww_clk_period <= clk_period;
ww_clk_state <= clk_state;
lock <= ww_lock;

gnd <= '0';
vcc <= '1';
GNDs <= (OTHERS => '0');
VCCs <= (OTHERS => '1');

\int_bar~I_modesel\ <= "00000000000000000000000001";
\clk_state~I_modesel\ <= "00000000000000000000000001";
\clk_state~clkctrl_modesel\ <= '0';
\now_state.st0~feeder_modesel\ <= "1001";
\now_state.st0~feeder_pathsel\ <= "00000000";
\clk_period~I_modesel\ <= "00000000000000000000000001";
\q0~feeder_modesel\ <= "1001";
\q0~feeder_pathsel\ <= "00001000";
reset_modesel <= "1001";
reset_pathsel <= "00000110";
\reset~clkctrl_modesel\ <= '0';
\now_state.st1~6_modesel\ <= "1001";
\now_state.st1~6_pathsel\ <= "00001000";
\wr_bar~feeder_modesel\ <= "1001";
\wr_bar~feeder_pathsel\ <= "00001000";
\now_state.st3~feeder_modesel\ <= "1001";
\now_state.st3~feeder_pathsel\ <= "00001000";
\now_state.st4~feeder_modesel\ <= "1001";
\now_state.st4~feeder_pathsel\ <= "00001000";
\now_state.st5~feeder_modesel\ <= "1001";
\now_state.st5~feeder_pathsel\ <= "00001000";
\Selector0~8_modesel\ <= "1001";
\Selector0~8_pathsel\ <= "00001101";
\now_state~34_modesel\ <= "1001";
\now_state~34_pathsel\ <= "00001001";
\rd_bar~0_modesel\ <= "1001";
\rd_bar~0_pathsel\ <= "00001100";
\lock~32_modesel\ <= "1001";
\lock~32_pathsel\ <= "00001100";
\wr_rdy~I_modesel\ <= "00000000000000000000000100";
\cs_bar~I_modesel\ <= "00000000000000000000000010";
\rd_bar~I_modesel\ <= "00000000000000000000000010";
\lock~I_modesel\ <= "00000000000000000000000010";

\reset~clkctrl_INCLK_bus\ <= (gnd & gnd & gnd & \reset~combout\);

\clk_state~clkctrl_INCLK_bus\ <= (gnd & gnd & gnd & \clk_state~combout\);

\INV_INST_rd_bar~reg0_regout\ : INV
PORT MAP (
	 IN1 => \rd_bar~reg0_regout\,
	 Y => \ALT_INV_rd_bar~reg0_regout\);

\INV_INST_wr_bar~regout\ : INV
PORT MAP (
	 IN1 => \wr_bar~regout\,
	 Y => \ALT_INV_wr_bar~regout\);

-- atom is at PIN_30
\int_bar~I\ : cycloneii_io
-- pragma translate_off
-- GENERIC MAP (
--	input_async_reset => "none",
--	input_power_up => "low",
--	input_register_mode => "none",
--	input_sync_reset => "none",
--	oe_async_reset => "none",
--	oe_power_up => "low",
--	oe_register_mode => "none",
--	oe_sync_reset => "none",
--	operation_mode => "input",
--	output_async_reset => "none",
--	output_power_up => "low",
--	output_register_mode => "none",
--	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	differentialin => GND,
	linkin => GND,
	modesel => \int_bar~I_modesel\,
	combout => \int_bar~combout\,
	padio => ww_int_bar);

-- atom is at PIN_23
\clk_state~I\ : cycloneii_io
-- pragma translate_off
-- GENERIC MAP (
--	input_async_reset => "none",
--	input_power_up => "low",
--	input_register_mode => "none",
--	input_sync_reset => "none",
--	oe_async_reset => "none",
--	oe_power_up => "low",
--	oe_register_mode => "none",
--	oe_sync_reset => "none",
--	operation_mode => "input",
--	output_async_reset => "none",
--	output_power_up => "low",
--	output_register_mode => "none",
--	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	differentialin => GND,
	linkin => GND,
	modesel => \clk_state~I_modesel\,
	combout => \clk_state~combout\,
	padio => ww_clk_state);

-- atom is at CLKCTRL_G2
\clk_state~clkctrl\ : cycloneii_clkctrl
-- pragma translate_off
-- GENERIC MAP (
--	clock_type => "global clock",
--	ena_register_mode => "falling edge")
-- pragma translate_on
PORT MAP (
	ena => VCC,
	inclk => \clk_state~clkctrl_INCLK_bus\,
	clkselect => GNDs(1 DOWNTO 0),
	modesel => \clk_state~clkctrl_modesel\,
	outclk => \clk_state~clkctrl_outclk\);

-- atom is at LCCOMB_X1_Y8_N10
\now_state.st0~feeder\ : cycloneii_lcell_comb
-- Equation(s):
-- \now_state.st0~feeder_combout\ = VCC

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "1111111111111111",
--	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	pathsel => \now_state.st0~feeder_pathsel\,
	dataa => VCC,
	datab => VCC,
	datac => VCC,
	datad => VCC,
	cin => GND,
	modesel => \now_state.st0~feeder_modesel\,
	combout => \now_state.st0~feeder_combout\);

-- atom is at PIN_35
\clk_period~I\ : cycloneii_io
-- pragma translate_off
-- GENERIC MAP (
--	input_async_reset => "none",
--	input_power_up => "low",
--	input_register_mode => "none",
--	input_sync_reset => "none",
--	oe_async_reset => "none",
--	oe_power_up => "low",
--	oe_register_mode => "none",
--	oe_sync_reset => "none",
--	operation_mode => "input",
--	output_async_reset => "none",
--	output_power_up => "low",
--	output_register_mode => "none",
--	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	differentialin => GND,
	linkin => GND,
	modesel => \clk_period~I_modesel\,
	combout => \clk_period~combout\,
	padio => ww_clk_period);

-- atom is at LCCOMB_X1_Y9_N4
\q0~feeder\ : cycloneii_lcell_comb
-- Equation(s):
-- \q0~feeder_combout\ = \clk_period~combout\

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "1111111100000000",
--	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	pathsel => \q0~feeder_pathsel\,
	dataa => VCC,
	datab => VCC,
	datac => VCC,
	datad => \clk_period~combout\,
	cin => GND,
	modesel => \q0~feeder_modesel\,
	combout => \q0~feeder_combout\);

-- atom is at LCFF_X1_Y9_N5
q0 : cycloneii_lcell_ff
PORT MAP (
	clk => \clk_state~clkctrl_outclk\,
	datain => \q0~feeder_combout\,
	sdata => GND,
	aclr => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	regout => \q0~regout\);

-- atom is at LCFF_X1_Y9_N21
q1 : cycloneii_lcell_ff
PORT MAP (
	clk => \clk_state~clkctrl_outclk\,
	datain => GND,
	sdata => \q0~regout\,
	aclr => GND,
	sclr => GND,
	sload => VCC,
	ena => VCC,
	regout => \q1~regout\);

-- atom is at LCCOMB_X1_Y9_N20
reset : cycloneii_lcell_comb
-- Equation(s):
-- \reset~combout\ = \q0~regout\ & !\q1~regout\

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "0000110000001100",
--	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	pathsel => reset_pathsel,
	dataa => VCC,
	datab => \q0~regout\,
	datac => \q1~regout\,
	datad => VCC,
	cin => GND,
	modesel => reset_modesel,
	combout => \reset~combout\);