adc_0820.vho

使用VHDL语言描述AD0809芯片功能

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 7.2 Build 151 09/26/2007 SJ Full Version"

-- DATE "05/20/2008 11:25:07"

-- 
-- Device: Altera EP2C8Q208C8 Package PQFP208
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, cycloneii;
USE IEEE.std_logic_1164.all;
USE cycloneii.cycloneii_components.all;

ENTITY 	ADC_0820 IS
    PORT (
	cs_bar : OUT std_logic;
	rd_bar : OUT std_logic;
	int_bar : IN std_logic;
	wr_rdy : INOUT std_logic;
	clk_period : IN std_logic;
	clk_state : IN std_logic;
	lock : OUT std_logic
	);
END ADC_0820;

ARCHITECTURE structure OF ADC_0820 IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_cs_bar : std_logic;
SIGNAL ww_rd_bar : std_logic;
SIGNAL ww_int_bar : std_logic;
SIGNAL ww_clk_period : std_logic;
SIGNAL ww_clk_state : std_logic;
SIGNAL ww_lock : std_logic;
SIGNAL \reset~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \clk_state~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \int_bar~combout\ : std_logic;
SIGNAL \clk_state~combout\ : std_logic;
SIGNAL \clk_state~clkctrl_outclk\ : std_logic;
SIGNAL \now_state.st0~feeder_combout\ : std_logic;
SIGNAL \clk_period~combout\ : std_logic;
SIGNAL \q0~feeder_combout\ : std_logic;
SIGNAL \q0~regout\ : std_logic;
SIGNAL \q1~regout\ : std_logic;
SIGNAL \reset~combout\ : std_logic;
SIGNAL \reset~clkctrl_outclk\ : std_logic;
SIGNAL \now_state.st0~regout\ : std_logic;
SIGNAL \now_state.st1~6_combout\ : std_logic;
SIGNAL \now_state.st1~regout\ : std_logic;
SIGNAL \wr_bar~feeder_combout\ : std_logic;
SIGNAL \wr_bar~regout\ : std_logic;
SIGNAL \now_state.st3~feeder_combout\ : std_logic;
SIGNAL \now_state.st3~regout\ : std_logic;
SIGNAL \now_state.st4~feeder_combout\ : std_logic;
SIGNAL \now_state.st4~regout\ : std_logic;
SIGNAL \now_state.st5~feeder_combout\ : std_logic;
SIGNAL \now_state.st5~regout\ : std_logic;
SIGNAL \Selector0~8_combout\ : std_logic;
SIGNAL \now_state.st6~regout\ : std_logic;
SIGNAL \now_state~34_combout\ : std_logic;
SIGNAL \now_state.st7~regout\ : std_logic;
SIGNAL \rd_bar~0_combout\ : std_logic;
SIGNAL \rd_bar~reg0_regout\ : std_logic;
SIGNAL \lock~32_combout\ : std_logic;
SIGNAL \lock~reg0_regout\ : std_logic;
SIGNAL \ALT_INV_rd_bar~reg0_regout\ : std_logic;
SIGNAL \ALT_INV_wr_bar~regout\ : std_logic;

BEGIN

cs_bar <= ww_cs_bar;
rd_bar <= ww_rd_bar;
ww_int_bar <= int_bar;
ww_clk_period <= clk_period;
ww_clk_state <= clk_state;
lock <= ww_lock;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

\reset~clkctrl_INCLK_bus\ <= (gnd & gnd & gnd & \reset~combout\);

\clk_state~clkctrl_INCLK_bus\ <= (gnd & gnd & gnd & \clk_state~combout\);
\ALT_INV_rd_bar~reg0_regout\ <= NOT \rd_bar~reg0_regout\;
\ALT_INV_wr_bar~regout\ <= NOT \wr_bar~regout\;

\int_bar~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_int_bar,
	combout => \int_bar~combout\);

\clk_state~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_clk_state,
	combout => \clk_state~combout\);

\clk_state~clkctrl\ : cycloneii_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "falling edge")
-- pragma translate_on
PORT MAP (
	inclk => \clk_state~clkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \clk_state~clkctrl_outclk\);

\now_state.st0~feeder\ : cycloneii_lcell_comb
-- Equation(s):
-- \now_state.st0~feeder_combout\ = VCC

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \now_state.st0~feeder_combout\);

\clk_period~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_clk_period,
	combout => \clk_period~combout\);

\q0~feeder\ : cycloneii_lcell_comb
-- Equation(s):
-- \q0~feeder_combout\ = \clk_period~combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \clk_period~combout\,
	combout => \q0~feeder_combout\);

q0 : cycloneii_lcell_ff
PORT MAP (
	clk => \clk_state~clkctrl_outclk\,
	datain => \q0~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \q0~regout\);

q1 : cycloneii_lcell_ff
PORT MAP (
	clk => \clk_state~clkctrl_outclk\,
	sdata => \q0~regout\,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \q1~regout\);

reset : cycloneii_lcell_comb
-- Equation(s):
-- \reset~combout\ = \q0~regout\ & !\q1~regout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000110000001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \q0~regout\,
	datac => \q1~regout\,
	combout => \reset~combout\);

\reset~clkctrl\ : cycloneii_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "falling edge")
-- pragma translate_on
PORT MAP (
	inclk => \reset~clkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \reset~clkctrl_outclk\);

\now_state.st0\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk_state~clkctrl_outclk\,
	datain => \now_state.st0~feeder_combout\,
	aclr => \reset~clkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \now_state.st0~regout\);

\now_state.st1~6\ : cycloneii_lcell_comb
-- Equation(s):
-- \now_state.st1~6_combout\ = !\now_state.st0~regout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \now_state.st0~regout\,
	combout => \now_state.st1~6_combout\);

\now_state.st1\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk_state~clkctrl_outclk\,