samkmorsy.vhf

VHDL实现的示波器-完整的文档和源代码

-- Vhdl model created from schematic samkmorsy.sch - Fri Jun 18 19:45:46 2004

LIBRARY ieee;
LIBRARY UNISIM;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE UNISIM.Vcomponents.ALL;

ENTITY samkmorsy IS
   PORT ( Q9	:	IN	STD_LOGIC; 
          clock	:	IN	STD_LOGIC; 
          data1	:	IN	STD_LOGIC_VECTOR (7 DOWNTO 0); 
          vclk	:	IN	STD_LOGIC; 
          RGB	:	OUT	STD_LOGIC_VECTOR (5 DOWNTO 0); 
          add2	:	OUT	STD_LOGIC_VECTOR (14 DOWNTO 0); 
          ena	:	OUT	STD_LOGIC; 
          hsync	:	OUT	STD_LOGIC; 
          oeb	:	OUT	STD_LOGIC; 
          read	:	OUT	STD_LOGIC; 
          red	:	OUT	STD_LOGIC; 
          reset	:	OUT	STD_LOGIC; 
          sel	:	OUT	STD_LOGIC; 
          vsync	:	OUT	STD_LOGIC; 
          web	:	OUT	STD_LOGIC; 
          data2	:	INOUT	STD_LOGIC_VECTOR (7 DOWNTO 0));

end samkmorsy;

ARCHITECTURE SCHEMATIC OF samkmorsy IS
   SIGNAL XLXN_15	:	STD_LOGIC;
   SIGNAL XLXN_16	:	STD_LOGIC;
   SIGNAL XLXN_17	:	STD_LOGIC;
   SIGNAL XLXN_23	:	STD_LOGIC;
   SIGNAL XLXN_24	:	STD_LOGIC;
   SIGNAL XLXN_3	:	STD_LOGIC_VECTOR (14 DOWNTO 0);
   SIGNAL XLXN_5	:	STD_LOGIC_VECTOR (14 DOWNTO 0);
   SIGNAL vdone	:	STD_LOGIC;

   ATTRIBUTE fpga_dont_touch : STRING ;

   COMPONENT control
      PORT ( Q_9	:	IN	STD_LOGIC; 
             V_done	:	IN	STD_LOGIC; 
             clr	:	IN	STD_LOGIC; 
             clk	:	IN	STD_LOGIC; 
             reset	:	OUT	STD_LOGIC; 
             sel	:	OUT	STD_LOGIC; 
             clk_conv	:	OUT	STD_LOGIC; 
             start	:	OUT	STD_LOGIC; 
             V_reset	:	OUT	STD_LOGIC; 
             en	:	OUT	STD_LOGIC; 
             enable	:	OUT	STD_LOGIC; 
             red	:	OUT	STD_LOGIC);
   END COMPONENT;

   COMPONENT convert
      PORT ( enable	:	IN	STD_LOGIC; 
             clk	:	IN	STD_LOGIC; 
             start	:	IN	STD_LOGIC; 
             data1	:	IN	STD_LOGIC_VECTOR (7 DOWNTO 0); 
             data2	:	INOUT	STD_LOGIC_VECTOR (7 DOWNTO 0); 
             read	:	OUT	STD_LOGIC; 
             oeb	:	OUT	STD_LOGIC; 
             web	:	OUT	STD_LOGIC; 
             clr	:	OUT	STD_LOGIC; 
             done	:	OUT	STD_LOGIC; 
             address	:	OUT	STD_LOGIC_VECTOR (14 DOWNTO 0));
   END COMPONENT;

   COMPONENT switch
      PORT ( Q_9	:	IN	STD_LOGIC; 
             vgadd	:	IN	STD_LOGIC_VECTOR (14 DOWNTO 0); 
             convadd	:	IN	STD_LOGIC_VECTOR (14 DOWNTO 0); 
             address2	:	OUT	STD_LOGIC_VECTOR (14 DOWNTO 0));
   END COMPONENT;

   COMPONENT vgacore
      PORT ( reset	:	IN	STD_LOGIC; 
             clock	:	IN	STD_LOGIC; 
             data	:	IN	STD_LOGIC_VECTOR (7 DOWNTO 0); 
             hsyncb	:	OUT	STD_LOGIC; 
             vsyncb	:	OUT	STD_LOGIC; 
             csb	:	OUT	STD_LOGIC; 
             oeb	:	OUT	STD_LOGIC; 
             web	:	OUT	STD_LOGIC; 
             rgb	:	OUT	STD_LOGIC_VECTOR (5 DOWNTO 0); 
             addr	:	OUT	STD_LOGIC_VECTOR (14 DOWNTO 0); 
             vdone	:	OUT	STD_LOGIC);
   END COMPONENT;

BEGIN

   XLXI_4 : control
      PORT MAP (Q_9=>Q9, V_done=>vdone, clr=>XLXN_24, clk=>clock, reset=>reset,
      sel=>sel, clk_conv=>XLXN_17, start=>XLXN_16, V_reset=>XLXN_23, en=>ena,
      enable=>XLXN_15, red=>red);

   XLXI_2 : convert
      PORT MAP (enable=>XLXN_15, clk=>XLXN_17, start=>XLXN_16,
      data1(7)=>data1(7), data1(6)=>data1(6), data1(5)=>data1(5),
      data1(4)=>data1(4), data1(3)=>data1(3), data1(2)=>data1(2),
      data1(1)=>data1(1), data1(0)=>data1(0), data2(7)=>data2(7),
      data2(6)=>data2(6), data2(5)=>data2(5), data2(4)=>data2(4),
      data2(3)=>data2(3), data2(2)=>data2(2), data2(1)=>data2(1),
      data2(0)=>data2(0), read=>read, oeb=>oeb, web=>web, clr=>XLXN_24,
      done=>open, address(14)=>XLXN_3(14), address(13)=>XLXN_3(13),
      address(12)=>XLXN_3(12), address(11)=>XLXN_3(11),
      address(10)=>XLXN_3(10), address(9)=>XLXN_3(9), address(8)=>XLXN_3(8),
      address(7)=>XLXN_3(7), address(6)=>XLXN_3(6), address(5)=>XLXN_3(5),
      address(4)=>XLXN_3(4), address(3)=>XLXN_3(3), address(2)=>XLXN_3(2),
      address(1)=>XLXN_3(1), address(0)=>XLXN_3(0));

   XLXI_1 : switch
      PORT MAP (Q_9=>Q9, vgadd(14)=>XLXN_5(14), vgadd(13)=>XLXN_5(13),
      vgadd(12)=>XLXN_5(12), vgadd(11)=>XLXN_5(11), vgadd(10)=>XLXN_5(10),
      vgadd(9)=>XLXN_5(9), vgadd(8)=>XLXN_5(8), vgadd(7)=>XLXN_5(7),
      vgadd(6)=>XLXN_5(6), vgadd(5)=>XLXN_5(5), vgadd(4)=>XLXN_5(4),
      vgadd(3)=>XLXN_5(3), vgadd(2)=>XLXN_5(2), vgadd(1)=>XLXN_5(1),
      vgadd(0)=>XLXN_5(0), convadd(14)=>XLXN_3(14), convadd(13)=>XLXN_3(13),
      convadd(12)=>XLXN_3(12), convadd(11)=>XLXN_3(11),
      convadd(10)=>XLXN_3(10), convadd(9)=>XLXN_3(9), convadd(8)=>XLXN_3(8),
      convadd(7)=>XLXN_3(7), convadd(6)=>XLXN_3(6), convadd(5)=>XLXN_3(5),
      convadd(4)=>XLXN_3(4), convadd(3)=>XLXN_3(3), convadd(2)=>XLXN_3(2),
      convadd(1)=>XLXN_3(1), convadd(0)=>XLXN_3(0), address2(14)=>add2(14),
      address2(13)=>add2(13), address2(12)=>add2(12), address2(11)=>add2(11),
      address2(10)=>add2(10), address2(9)=>add2(9), address2(8)=>add2(8),
      address2(7)=>add2(7), address2(6)=>add2(6), address2(5)=>add2(5),
      address2(4)=>add2(4), address2(3)=>add2(3), address2(2)=>add2(2),
      address2(1)=>add2(1), address2(0)=>add2(0));

   XLXI_3 : vgacore
      PORT MAP (reset=>XLXN_23, clock=>vclk, data(7)=>data2(7),
      data(6)=>data2(6), data(5)=>data2(5), data(4)=>data2(4),
      data(3)=>data2(3), data(2)=>data2(2), data(1)=>data2(1),
      data(0)=>data2(0), hsyncb=>hsync, vsyncb=>vsync, csb=>open, oeb=>open,
      web=>open, rgb(5)=>RGB(5), rgb(4)=>RGB(4), rgb(3)=>RGB(3),
      rgb(2)=>RGB(2), rgb(1)=>RGB(1), rgb(0)=>RGB(0), addr(14)=>XLXN_5(14),
      addr(13)=>XLXN_5(13), addr(12)=>XLXN_5(12), addr(11)=>XLXN_5(11),
      addr(10)=>XLXN_5(10), addr(9)=>XLXN_5(9), addr(8)=>XLXN_5(8),
      addr(7)=>XLXN_5(7), addr(6)=>XLXN_5(6), addr(5)=>XLXN_5(5),
      addr(4)=>XLXN_5(4), addr(3)=>XLXN_5(3), addr(2)=>XLXN_5(2),
      addr(1)=>XLXN_5(1), addr(0)=>XLXN_5(0), vdone=>vdone);

END SCHEMATIC;