gate_control.tan.qmsg

来自「采用VerilogHDL语言编写的数字频率计」· QMSG 代码 · 共 15 行 · 第 1/5 页

{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dp_s100hz\$latch~10 " "Info: Node \"dp_s100hz\$latch~10\"" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0}  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dp_s10hz\$latch~10 " "Info: Node \"dp_s10hz\$latch~10\"" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0}  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dp_s1hz\$latch~10 " "Info: Node \"dp_s1hz\$latch~10\"" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0}  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0}