data_mux.hier_info

采用VerilogHDL语言编写的数字频率计

|data_mux
disp_select[0] => Decoder~0.IN2
disp_select[1] => Decoder~0.IN1
disp_select[2] => Decoder~0.IN0
A0[0] => Select~3.IN1
A0[1] => Select~2.IN1
A0[2] => Select~1.IN1
A0[3] => Select~0.IN1
A1[0] => Select~3.IN2
A1[1] => Select~2.IN2
A1[2] => Select~1.IN2
A1[3] => Select~0.IN2
A2[0] => Select~3.IN3
A2[1] => Select~2.IN3
A2[2] => Select~1.IN3
A2[3] => Select~0.IN3
A3[0] => Select~3.IN4
A3[1] => Select~2.IN4
A3[2] => Select~1.IN4
A3[3] => Select~0.IN4
A4[0] => Select~3.IN5
A4[1] => Select~2.IN5
A4[2] => Select~1.IN5
A4[3] => Select~0.IN5
A5[0] => Select~3.IN6
A5[1] => Select~2.IN6
A5[2] => Select~1.IN6
A5[3] => Select~0.IN6
Q[0] <= Select~3.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= Select~2.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= Select~1.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= Select~0.DB_MAX_OUTPUT_PORT_TYPE