data_mux.tan.qmsg

采用VerilogHDL语言编写的数字频率计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 17 22:48:48 2006 " "Info: Processing started: Mon Jul 17 22:48:48 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off data_mux -c data_mux " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off data_mux -c data_mux" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "disp_select\[0\] Q\[0\] 5.900 ns Longest " "Info: Longest tpd from source pin \"disp_select\[0\]\" to destination pin \"Q\[0\]\" is 5.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns disp_select\[0\] 1 PIN PIN_44 24 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_44; Fanout = 24; PIN Node = 'disp_select\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/data_mux/db/data_mux_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/data_mux/db/data_mux_cmp.qrpt" Compiler "data_mux" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/data_mux/db/data_mux.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/data_mux/" "" "" { disp_select[0] } "NODE_NAME" } "" } } { "data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/data_mux/data_mux.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.600 ns) 3.800 ns Select~1552 2 COMB LC1 1 " "Info: 2: + IC(0.000 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC1; Fanout = 1; COMB Node = 'Select~1552'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/data_mux/db/data_mux_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/data_mux/db/data_mux_cmp.qrpt" Compiler "data_mux" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/data_mux/db/data_mux.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/data_mux/" "" "2.600 ns" { disp_select[0] Select~1552 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 5.700 ns Select~1545 3 COMB LC2 1 " "Info: 3: + IC(0.000 ns) + CELL(1.900 ns) = 5.700 ns; Loc. = LC2; Fanout = 1; COMB Node = 'Select~1545'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/data_mux/db/data_mux_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/data_mux/db/data_mux_cmp.qrpt" Compiler "data_mux" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/data_mux/db/data_mux.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/data_mux/" "" "1.900 ns" { Select~1552 Select~1545 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 5.900 ns Q\[0\] 4 PIN PIN_5 0 " "Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 5.900 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'Q\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/data_mux/db/data_mux_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/data_mux/db/data_mux_cmp.qrpt" Compiler "data_mux" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/data_mux/db/data_mux.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/data_mux/" "" "0.200 ns" { Select~1545 Q[0] } "NODE_NAME" } "" } } { "data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/data_mux/data_mux.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.900 ns 100.00 % " "Info: Total cell delay = 5.900 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/data_mux/db/data_mux_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/data_mux/db/data_mux_cmp.qrpt" Compiler "data_mux" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/data_mux/db/data_mux.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/data_mux/" "" "5.900 ns" { disp_select[0] Select~1552 Select~1545 Q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.900 ns" { disp_select[0] disp_select[0]~out Select~1552 Select~1545 Q[0] } { 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 2.600ns 1.900ns 0.200ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 17 22:48:48 2006 " "Info: Processing ended: Mon Jul 17 22:48:48 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}