fdiv.tan.qmsg

采用VerilogHDL语言编写的数字频率计

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "f10hz~reg0 " "Info: Detected ripple clock \"f10hz~reg0\" as buffer" {  } { { "fdiv.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/fdiv.v" 52 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "f10hz~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "f100hz~reg0 " "Info: Detected ripple clock \"f100hz~reg0\" as buffer" {  } { { "fdiv.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/fdiv.v" 37 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "f100hz~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "f1khz~reg0 " "Info: Detected ripple clock \"f1khz~reg0\" as buffer" {  } { { "fdiv.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/fdiv.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "f1khz~reg0" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lpm_counter:cnt2_rtl_2\|dffs\[2\] register lpm_counter:cnt2_rtl_2\|dffs\[15\] 144.93 MHz 6.9 ns Internal " "Info: Clock \"clk\" has Internal fmax of 144.93 MHz between source register \"lpm_counter:cnt2_rtl_2\|dffs\[2\]\" and destination register \"lpm_counter:cnt2_rtl_2\|dffs\[15\]\" (period= 6.9 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.600 ns + Longest register register " "Info: + Longest register to register delay is 4.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:cnt2_rtl_2\|dffs\[2\] 1 REG LC129 34 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC129; Fanout = 34; REG Node = 'lpm_counter:cnt2_rtl_2\|dffs\[2\]'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/" "" "" { lpm_counter:cnt2_rtl_2|dffs[2] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(2.800 ns) 4.600 ns lpm_counter:cnt2_rtl_2\|dffs\[15\] 2 REG LC74 21 " "Info: 2: + IC(1.800 ns) + CELL(2.800 ns) = 4.600 ns; Loc. = LC74; Fanout = 21; REG Node = 'lpm_counter:cnt2_rtl_2\|dffs\[15\]'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/" "" "4.600 ns" { lpm_counter:cnt2_rtl_2|dffs[2] lpm_counter:cnt2_rtl_2|dffs[15] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 60.87 % " "Info: Total cell delay = 2.800 ns ( 60.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.800 ns 39.13 % " "Info: Total interconnect delay = 1.800 ns ( 39.13 % )" {  } {  } 0}  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/" "" "4.600 ns" { lpm_counter:cnt2_rtl_2|dffs[2] lpm_counter:cnt2_rtl_2|dffs[15] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.600 ns" { lpm_counter:cnt2_rtl_2|dffs[2] lpm_counter:cnt2_rtl_2|dffs[15] } { 0.000ns 1.800ns } { 0.000ns 2.800ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.200 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 8.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns clk 1 CLK PIN_83 33 " "Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/" "" "" { clk } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/fdiv.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.700 ns) 3.500 ns f1khz~reg0 2 REG LC51 34 " "Info: 2: + IC(0.000 ns) + CELL(1.700 ns) = 3.500 ns; Loc. = LC51; Fanout = 34; REG Node = 'f1khz~reg0'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/" "" "1.700 ns" { clk f1khz~reg0 } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/fdiv.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(2.900 ns) 8.200 ns lpm_counter:cnt2_rtl_2\|dffs\[15\] 3 REG LC74 21 " "Info: 3: + IC(1.800 ns) + CELL(2.900 ns) = 8.200 ns; Loc. = LC74; Fanout = 21; REG Node = 'lpm_counter:cnt2_rtl_2\|dffs\[15\]'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/" "" "4.700 ns" { f1khz~reg0 lpm_counter:cnt2_rtl_2|dffs[15] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.400 ns 78.05 % " "Info: Total cell delay = 6.400 ns ( 78.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.800 ns 21.95 % " "Info: Total interconnect delay = 1.800 ns ( 21.95 % )" {  } {  } 0}  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/" "" "8.200 ns" { clk f1khz~reg0 lpm_counter:cnt2_rtl_2|dffs[15] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.200 ns" { clk clk~out f1khz~reg0 lpm_counter:cnt2_rtl_2|dffs[15] } { 0.000ns 0.000ns 0.000ns 1.800ns } { 0.000ns 1.800ns 1.700ns 2.900ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.200 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns clk 1 CLK PIN_83 33 " "Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/" "" "" { clk } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/fdiv.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.700 ns) 3.500 ns f1khz~reg0 2 REG LC51 34 " "Info: 2: + IC(0.000 ns) + CELL(1.700 ns) = 3.500 ns; Loc. = LC51; Fanout = 34; REG Node = 'f1khz~reg0'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/" "" "1.700 ns" { clk f1khz~reg0 } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/fdiv.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(2.900 ns) 8.200 ns lpm_counter:cnt2_rtl_2\|dffs\[2\] 3 REG LC129 34 " "Info: 3: + IC(1.800 ns) + CELL(2.900 ns) = 8.200 ns; Loc. = LC129; Fanout = 34; REG Node = 'lpm_counter:cnt2_rtl_2\|dffs\[2\]'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/" "" "4.700 ns" { f1khz~reg0 lpm_counter:cnt2_rtl_2|dffs[2] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.400 ns 78.05 % " "Info: Total cell delay = 6.400 ns ( 78.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.800 ns 21.95 % " "Info: Total interconnect delay = 1.800 ns ( 21.95 % )" {  } {  } 0}  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/" "" "8.200 ns" { clk f1khz~reg0 lpm_counter:cnt2_rtl_2|dffs[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.200 ns" { clk clk~out f1khz~reg0 lpm_counter:cnt2_rtl_2|dffs[2] } { 0.000ns 0.000ns 0.000ns 1.800ns } { 0.000ns 1.800ns 1.700ns 2.900ns } } }  } 0}  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/" "" "8.200 ns" { clk f1khz~reg0 lpm_counter:cnt2_rtl_2|dffs[15] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.200 ns" { clk clk~out f1khz~reg0 lpm_counter:cnt2_rtl_2|dffs[15] } { 0.000ns 0.000ns 0.000ns 1.800ns } { 0.000ns 1.800ns 1.700ns 2.900ns } } } { "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/" "" "8.200 ns" { clk f1khz~reg0 lpm_counter:cnt2_rtl_2|dffs[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.200 ns" { clk clk~out f1khz~reg0 lpm_counter:cnt2_rtl_2|dffs[2] } { 0.000ns 0.000ns 0.000ns 1.800ns } { 0.000ns 1.800ns 1.700ns 2.900ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0}  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/" "" "4.600 ns" { lpm_counter:cnt2_rtl_2|dffs[2] lpm_counter:cnt2_rtl_2|dffs[15] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.600 ns" { lpm_counter:cnt2_rtl_2|dffs[2] lpm_counter:cnt2_rtl_2|dffs[15] } { 0.000ns 1.800ns } { 0.000ns 2.800ns } } } { "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/" "" "8.200 ns" { clk f1khz~reg0 lpm_counter:cnt2_rtl_2|dffs[15] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.200 ns" { clk clk~out f1khz~reg0 lpm_counter:cnt2_rtl_2|dffs[15] } { 0.000ns 0.000ns 0.000ns 1.800ns } { 0.000ns 1.800ns 1.700ns 2.900ns } } } { "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/" "" "8.200 ns" { clk f1khz~reg0 lpm_counter:cnt2_rtl_2|dffs[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.200 ns" { clk clk~out f1khz~reg0 lpm_counter:cnt2_rtl_2|dffs[2] } { 0.000ns 0.000ns 0.000ns 1.800ns } { 0.000ns 1.800ns 1.700ns 2.900ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk f1hz f1hz~reg0 21.900 ns register " "Info: tco from clock \"clk\" to destination pin \"f1hz\" through register \"f1hz~reg0\" is 21.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 20.200 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 20.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns clk 1 CLK PIN_83 33 " "Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/" "" "" { clk } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/fdiv.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.700 ns) 3.500 ns f1khz~reg0 2 REG LC51 34 " "Info: 2: + IC(0.000 ns) + CELL(1.700 ns) = 3.500 ns; Loc. = LC51; Fanout = 34; REG Node = 'f1khz~reg0'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/" "" "1.700 ns" { clk f1khz~reg0 } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/fdiv.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(4.200 ns) 9.500 ns f100hz~reg0 3 REG LC1 34 " "Info: 3: + IC(1.800 ns) + CELL(4.200 ns) = 9.500 ns; Loc. = LC1; Fanout = 34; REG Node = 'f100hz~reg0'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/" "" "6.000 ns" { f1khz~reg0 f100hz~reg0 } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/fdiv.v" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(4.200 ns) 15.500 ns f10hz~reg0 4 REG LC17 34 " "Info: 4: + IC(1.800 ns) + CELL(4.200 ns) = 15.500 ns; Loc. = LC17; Fanout = 34; REG Node = 'f10hz~reg0'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/" "" "6.000 ns" { f100hz~reg0 f10hz~reg0 } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/fdiv.v" 52 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(2.900 ns) 20.200 ns f1hz~reg0 5 REG LC35 1 " "Info: 5: + IC(1.800 ns) + CELL(2.900 ns) = 20.200 ns; Loc. = LC35; Fanout = 1; REG Node = 'f1hz~reg0'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/" "" "4.700 ns" { f10hz~reg0 f1hz~reg0 } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/fdiv.v" 67 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.800 ns 73.27 % " "Info: Total cell delay = 14.800 ns ( 73.27 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.400 ns 26.73 % " "Info: Total interconnect delay = 5.400 ns ( 26.73 % )" {  } {  } 0}  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/" "" "20.200 ns" { clk f1khz~reg0 f100hz~reg0 f10hz~reg0 f1hz~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "20.200 ns" { clk clk~out f1khz~reg0 f100hz~reg0 f10hz~reg0 f1hz~reg0 } { 0.000ns 0.000ns 0.000ns 1.800ns 1.800ns 1.800ns } { 0.000ns 1.800ns 1.700ns 4.200ns 4.200ns 2.900ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "fdiv.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/fdiv.v" 67 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.400 ns + Longest register pin " "Info: + Longest register to pin delay is 0.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns f1hz~reg0 1 REG LC35 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC35; Fanout = 1; REG Node = 'f1hz~reg0'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/" "" "" { f1hz~reg0 } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/fdiv.v" 67 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 0.400 ns f1hz 2 PIN PIN_25 0 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 0.400 ns; Loc. = PIN_25; Fanout = 0; PIN Node = 'f1hz'" {  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/" "" "0.400 ns" { f1hz~reg0 f1hz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/fdiv.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.400 ns 100.00 % " "Info: Total cell delay = 0.400 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/" "" "0.400 ns" { f1hz~reg0 f1hz } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.400 ns" { f1hz~reg0 f1hz } { 0.000ns 0.000ns } { 0.000ns 0.400ns } } }  } 0}  } { { "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/" "" "20.200 ns" { clk f1khz~reg0 f100hz~reg0 f10hz~reg0 f1hz~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "20.200 ns" { clk clk~out f1khz~reg0 f100hz~reg0 f10hz~reg0 f1hz~reg0 } { 0.000ns 0.000ns 0.000ns 1.800ns 1.800ns 1.800ns } { 0.000ns 1.800ns 1.700ns 4.200ns 4.200ns 2.900ns } } } { "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/书/Verilog书/源代码/cymometer/fdiv/" "" "0.400 ns" { f1hz~reg0 f1hz } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.400 ns" { f1hz~reg0 f1hz } { 0.000ns 0.000ns } { 0.000ns 0.400ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 10 22:01:41 2006 " "Info: Processing ended: Mon Jul 10 22:01:41 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}