fir_16.map.rpt

fir滤波器-verilog

+--------------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                                                                          ;
+---------------+---------------------------+------------------------------------------------------------------------------------------+
; Register name ; Reason for Removal        ; Registers Removed due to This Register                                                   ;
+---------------+---------------------------+------------------------------------------------------------------------------------------+
; OUT_r[15][15] ; Stuck at GND              ; Xk_i[0]~reg0, Xk_r[15]~reg0, Xk_r[14]~reg0, Xk_r[13]~reg0, Xk_r[12]~reg0, Xk_r[11]~reg0, ;
;               ; due to stuck port data_in ; Xk_r[10]~reg0, Xk_r[9]~reg0, Xk_r[8]~reg0, Xk_r[7]~reg0, Xk_r[6]~reg0, Xk_r[5]~reg0,     ;
;               ;                           ; Xk_r[4]~reg0, Xk_r[3]~reg0, Xk_r[2]~reg0, Xk_r[1]~reg0, Xk_r[0]~reg0, Xk_i[15]~reg0,     ;
;               ;                           ; Xk_i[14]~reg0, Xk_i[13]~reg0, Xk_i[12]~reg0, Xk_i[11]~reg0, Xk_i[10]~reg0, Xk_i[9]~reg0, ;
;               ;                           ; Xk_i[8]~reg0, Xk_i[7]~reg0, Xk_i[6]~reg0, Xk_i[5]~reg0, Xk_i[4]~reg0, Xk_i[3]~reg0,      ;
;               ;                           ; Xk_i[2]~reg0, Xk_i[1]~reg0                                                               ;
; p[2]          ; Stuck at GND              ; l[2], l[1], l[0]                                                                         ;
;               ; due to stuck port data_in ;                                                                                          ;
+---------------+---------------------------+------------------------------------------------------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 2 bits    ; 4 LEs         ; 0 LEs                ; 4 LEs                  ; Yes        ; |fft_16|l[1]               ;
; 4:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |fft_16|p[2]               ;
; 4:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; Yes        ; |fft_16|i[4]               ;
; 8:1                ; 3 bits    ; 15 LEs        ; 6 LEs                ; 9 LEs                  ; Yes        ; |fft_16|n[2]               ;
; 11:1               ; 3 bits    ; 21 LEs        ; 6 LEs                ; 15 LEs                 ; No         ; |fft_16|Selector4          ;
; 12:1               ; 2 bits    ; 16 LEs        ; 6 LEs                ; 10 LEs                 ; No         ; |fft_16|Selector1          ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |fft_16 ;
+----------------+-------+-----------------------------------------------+
; Parameter Name ; Value ; Type                                          ;
+----------------+-------+-----------------------------------------------+
; Idle           ; 000   ; Unsigned Binary                               ;
; Input          ; 001   ; Unsigned Binary                               ;
; Compute0       ; 010   ; Unsigned Binary                               ;
; Compute1       ; 100   ; Unsigned Binary                               ;
; Butfly         ; 101   ; Unsigned Binary                               ;
; Output         ; 110   ; Unsigned Binary                               ;
+----------------+-------+-----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Thu Oct 16 15:04:41 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fir_16 -c fir_16
Info: Found 1 design units, including 1 entities, in source file fft_16.v
    Info: Found entity 1: fft_16
Info: Elaborating entity "fft_16" for the top level hierarchy
Warning (10858): Verilog HDL warning at fft_16.v(11): object OUT1 used but never assigned
Warning (10036): Verilog HDL or VHDL warning at fft_16.v(11): object "STRT1" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at fft_16.v(17): object "TRANIN_r" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at fft_16.v(17): object "TRANIN_i" assigned a value but never read
Warning (10858): Verilog HDL warning at fft_16.v(18): object TRANOUT_r used but never assigned
Warning (10858): Verilog HDL warning at fft_16.v(18): object TRANOUT_i used but never assigned
Warning (10230): Verilog HDL assignment warning at fft_16.v(102): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at fft_16.v(124): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at fft_16.v(132): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at fft_16.v(138): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at fft_16.v(151): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at fft_16.v(186): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at fft_16.v(188): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at fft_16.v(194): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at fft_16.v(195): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at fft_16.v(197): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at fft_16.v(219): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at fft_16.v(220): truncated value with size 32 to match size of target (3)
Warning (10030): Net "OUT1" at fft_16.v(11) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_r[15]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_r[14]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_r[13]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_r[12]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_r[11]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_r[10]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_r[9]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_r[8]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_r[7]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_r[6]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_r[5]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_r[4]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_r[3]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_r[2]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_r[1]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_r[0]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_i[15]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_i[14]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_i[13]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_i[12]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_i[11]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_i[10]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_i[9]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_i[8]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_i[7]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_i[6]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_i[5]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_i[4]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_i[3]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_i[2]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_i[1]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "TRANOUT_i[0]" at fft_16.v(18) has no driver or initial value, using a default initial value '0'
Info: Duplicate registers merged to single register
    Info: Duplicate register "OUT_r[3][2]" merged to single register "OUT_r[15][15]"
    Info: Duplicate register "OUT_i[6][2]" merged to single register "OUT_r[15][15]"
    Info: Duplicate register "OUT_r[15][4]" merged to single register "OUT_r[15][15]"
    Info: Duplicate register "OUT_i[6][0]" merged to single register "OUT_r[15][15]"
    Info: Duplicate register "OUT_r[3][0]" merged to single register "OUT_r[15][15]"
    Info: Duplicate register "OUT_i[5][14]" merged to single register "OUT_r[15][15]"
    Info: Duplicate register "OUT_r[9][8]" merged to single register "OUT_r[15][15]"
    Info: Duplicate register "OUT_i[5][12]" merged to single register "OUT_r[15][15]"
    Info: Duplicate register "OUT_r[2][14]" merged to single register "OUT_r[15][15]"
    Info: Duplicate register "OUT_i[5][10]" merged to single register "OUT_r[15][15]"
    Info: Duplicate register "OUT_r[12][12]" merged to single register "OUT_r[15][15]"
    Info: Duplicate register "OUT_i[5][8]" merged to single register "OUT_r[15][15]"
    Info: Duplicate register "OUT_r[2][12]" merged to single register "OUT_r[15][15]"
    Info: Duplicate register "OUT_i[5][6]" merged to single register "OUT_r[15][15]"
    Info: Duplicate register "OUT_r[9][6]" merged to single register "OUT_r[15][15]"
    Info: Duplicate register "OUT_i[5][4]" merged to single register "OUT_r[15][15]"
    Info: Duplicate register "OUT_r[2][10]" merged to single register "OUT_r[15][15]"
    Info: Duplicate register "OUT_i[5][2]" merged to single register "OUT_r[15][15]"
    Info: Duplicate register "OUT_r[14][6]" merged to single register "OUT_r[15][15]"
    Info: Duplicate register "OUT_i[5][0]" merged to single register "OUT_r[15][15]"
    Info: Duplicate register "OUT_r[2][8]" merged to single register "OUT_r[15][15]"
    Info: Duplicate register "OUT_i[4][14]" merged to single register "OUT_r[15][15]"
    Info: Duplicate register "OUT_r[9][4]" merged to single register "OUT_r[15][15]"
    Info: Duplicate register "OUT_i[4][12]" merged to single register "OUT_r[15][15]"
    Info: Duplicate register "OUT_r[2][6]" merged to single register "OUT_r[15][15]"
    Info: Duplicate register "OUT_i[4][10]" merged to single register "OUT_r[15][15]"
    Info: Duplicate register "OUT_r[12][10]" merged to single register "OUT_r[15][15]"
    Info: Duplicate register "OUT_i[4][8]" merged to single register "OUT_r[15][15]"