📄 fir_16.map.rpt
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; -- 1 input functions ; 0 ;
; -- 0 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 0 ;
; -- arithmetic mode ; 0 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 0 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 0 ;
; I/O pins ; 68 ;
+---------------------------------------------+-------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |fft_16 ; 0 (0) ; 0 ; 0 ; 68 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |fft_16 ; work ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
Encoding Type: One-Hot
+-----------------------------------------------------------------------------------------------------------+
; State Machine - |fft_16|state ;
+----------------+--------------+--------------+----------------+----------------+-------------+------------+
; Name ; state.Output ; state.Butfly ; state.Compute1 ; state.Compute0 ; state.Input ; state.Idle ;
+----------------+--------------+--------------+----------------+----------------+-------------+------------+
; state.Idle ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; state.Input ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;
; state.Compute0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;
; state.Compute1 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;
; state.Butfly ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;
; state.Output ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;
+----------------+--------------+--------------+----------------+----------------+-------------+------------+
+---------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+-----------------------------------------+---------------------------+
; Register name ; Reason for Removal ;
+-----------------------------------------+---------------------------+
; OUT_r[3][2] ; Merged with OUT_r[15][15] ;
; OUT_i[6][2] ; Merged with OUT_r[15][15] ;
; OUT_r[15][4] ; Merged with OUT_r[15][15] ;
; OUT_i[6][0] ; Merged with OUT_r[15][15] ;
; OUT_r[3][0] ; Merged with OUT_r[15][15] ;
; OUT_i[5][14] ; Merged with OUT_r[15][15] ;
; OUT_r[9][8] ; Merged with OUT_r[15][15] ;
; OUT_i[5][12] ; Merged with OUT_r[15][15] ;
; OUT_r[2][14] ; Merged with OUT_r[15][15] ;
; OUT_i[5][10] ; Merged with OUT_r[15][15] ;
; OUT_r[12][12] ; Merged with OUT_r[15][15] ;
; OUT_i[5][8] ; Merged with OUT_r[15][15] ;
; OUT_r[2][12] ; Merged with OUT_r[15][15] ;
; OUT_i[5][6] ; Merged with OUT_r[15][15] ;
; OUT_r[9][6] ; Merged with OUT_r[15][15] ;
; OUT_i[5][4] ; Merged with OUT_r[15][15] ;
; OUT_r[2][10] ; Merged with OUT_r[15][15] ;
; OUT_i[5][2] ; Merged with OUT_r[15][15] ;
; OUT_r[14][6] ; Merged with OUT_r[15][15] ;
; OUT_i[5][0] ; Merged with OUT_r[15][15] ;
; OUT_r[2][8] ; Merged with OUT_r[15][15] ;
; OUT_i[4][14] ; Merged with OUT_r[15][15] ;
; OUT_r[9][4] ; Merged with OUT_r[15][15] ;
; OUT_i[4][12] ; Merged with OUT_r[15][15] ;
; OUT_r[2][6] ; Merged with OUT_r[15][15] ;
; OUT_i[4][10] ; Merged with OUT_r[15][15] ;
; OUT_r[12][10] ; Merged with OUT_r[15][15] ;
; OUT_i[4][8] ; Merged with OUT_r[15][15] ;
; OUT_r[2][4] ; Merged with OUT_r[15][15] ;
; OUT_i[4][6] ; Merged with OUT_r[15][15] ;
; OUT_r[9][2] ; Merged with OUT_r[15][15] ;
; OUT_i[4][4] ; Merged with OUT_r[15][15] ;
; OUT_r[2][2] ; Merged with OUT_r[15][15] ;
; OUT_i[4][2] ; Merged with OUT_r[15][15] ;
; OUT_r[15][10] ; Merged with OUT_r[15][15] ;
; OUT_i[4][0] ; Merged with OUT_r[15][15] ;
; OUT_r[2][0] ; Merged with OUT_r[15][15] ;
; OUT_i[3][14] ; Merged with OUT_r[15][15] ;
; OUT_r[9][0] ; Merged with OUT_r[15][15] ;
; OUT_i[3][12] ; Merged with OUT_r[15][15] ;
; OUT_r[1][14] ; Merged with OUT_r[15][15] ;
; OUT_i[3][10] ; Merged with OUT_r[15][15] ;
; OUT_r[12][8] ; Merged with OUT_r[15][15] ;
; OUT_i[3][8] ; Merged with OUT_r[15][15] ;
; OUT_r[1][12] ; Merged with OUT_r[15][15] ;
; OUT_i[3][6] ; Merged with OUT_r[15][15] ;
; OUT_r[8][14] ; Merged with OUT_r[15][15] ;
; OUT_i[3][4] ; Merged with OUT_r[15][15] ;
; OUT_r[1][10] ; Merged with OUT_r[15][15] ;
; OUT_i[3][2] ; Merged with OUT_r[15][15] ;
; OUT_r[14][4] ; Merged with OUT_r[15][15] ;
; OUT_i[3][0] ; Merged with OUT_r[15][15] ;
; OUT_r[1][8] ; Merged with OUT_r[15][15] ;
; OUT_i[2][14] ; Merged with OUT_r[15][15] ;
; OUT_r[8][12] ; Merged with OUT_r[15][15] ;
; OUT_i[2][12] ; Merged with OUT_r[15][15] ;
; OUT_r[1][6] ; Merged with OUT_r[15][15] ;
; OUT_i[2][10] ; Merged with OUT_r[15][15] ;
; OUT_r[12][6] ; Merged with OUT_r[15][15] ;
; OUT_i[2][8] ; Merged with OUT_r[15][15] ;
; OUT_r[1][4] ; Merged with OUT_r[15][15] ;
; OUT_i[2][6] ; Merged with OUT_r[15][15] ;
; OUT_r[8][10] ; Merged with OUT_r[15][15] ;
; OUT_i[2][4] ; Merged with OUT_r[15][15] ;
; OUT_r[1][2] ; Merged with OUT_r[15][15] ;
; OUT_i[2][2] ; Merged with OUT_r[15][15] ;
; OUT_r[15][2] ; Merged with OUT_r[15][15] ;
; OUT_i[2][0] ; Merged with OUT_r[15][15] ;
; OUT_r[1][0] ; Merged with OUT_r[15][15] ;
; OUT_i[1][14] ; Merged with OUT_r[15][15] ;
; OUT_r[8][8] ; Merged with OUT_r[15][15] ;
; OUT_i[1][12] ; Merged with OUT_r[15][15] ;
; OUT_r[0][14] ; Merged with OUT_r[15][15] ;
; OUT_i[1][10] ; Merged with OUT_r[15][15] ;
; OUT_r[12][4] ; Merged with OUT_r[15][15] ;
; OUT_i[1][8] ; Merged with OUT_r[15][15] ;
; OUT_r[0][12] ; Merged with OUT_r[15][15] ;
; OUT_i[1][6] ; Merged with OUT_r[15][15] ;
; OUT_r[8][6] ; Merged with OUT_r[15][15] ;
; OUT_i[1][4] ; Merged with OUT_r[15][15] ;
; OUT_r[0][10] ; Merged with OUT_r[15][15] ;
; OUT_i[1][2] ; Merged with OUT_r[15][15] ;
; OUT_r[14][2] ; Merged with OUT_r[15][15] ;
; OUT_i[1][0] ; Merged with OUT_r[15][15] ;
; OUT_r[0][8] ; Merged with OUT_r[15][15] ;
; OUT_i[0][14] ; Merged with OUT_r[15][15] ;
; OUT_r[8][4] ; Merged with OUT_r[15][15] ;
; OUT_i[0][12] ; Merged with OUT_r[15][15] ;
; OUT_r[0][6] ; Merged with OUT_r[15][15] ;
; OUT_i[0][10] ; Merged with OUT_r[15][15] ;
; OUT_r[12][2] ; Merged with OUT_r[15][15] ;
; OUT_i[0][8] ; Merged with OUT_r[15][15] ;
; OUT_r[0][4] ; Merged with OUT_r[15][15] ;
; OUT_i[0][6] ; Merged with OUT_r[15][15] ;
; OUT_r[8][2] ; Merged with OUT_r[15][15] ;
; OUT_i[0][4] ; Merged with OUT_r[15][15] ;
; OUT_r[0][2] ; Merged with OUT_r[15][15] ;
; OUT_r[0][0] ; Merged with OUT_r[15][15] ;
; OUT_i[0][2] ; Merged with OUT_r[15][15] ;
; OUT_r[15][13] ; Merged with OUT_r[15][15] ;
; Total Number of Removed Registers = 569 ; ;
+-----------------------------------------+---------------------------+
* Table truncated at 100 items. To change the number of removed registers reported, set the "Number of Removed Registers Reported" option under Assignments->Settings->Analysis and Synthesis Settings->More Settings
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